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參數(shù)資料
| 型號： | SCF5250VM120 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 54/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT 120MHZ AUD 196-MAPBGA |
| 產品變化通告： | Product Discontinuation 24/Feb/2012 |
| 標準包裝： | 126 |
| 系列： | SCF52xx |
| 核心處理器： | Coldfire V2 |
| 芯體尺寸： | 32-位 |
| 速度： | 120MHz |
| 連通性： | EBI/EMI，I²C，IDE，MMC，SPI，UART/USART |
| 外圍設備： | DMA，I²S，POR，串行音頻，WDT |
| 輸入/輸出數(shù)： | 57 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.08 V ~ 1.32 V |
| 數(shù)據(jù)轉換器： | A/D 6x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -20°C ~ 70°C |
| 封裝/外殼： | 196-LBGA |
| 包裝： | 托盤 |
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SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
7
1.2.22
JTAG
To help with system diagnostics and manufacturing testing, the SCF5250 includes dedicated
user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability,
often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A
standard. Freescale provides BSDL files for JTAG testing.
1.2.23
System Debug Interface
The ColdFire processor core debug interface supports real-time instruction trace and debug, plus
background-debug mode. A background-debug mode (BDM) interface provides system debug.
In real-time instruction trace, four status lines provide information on processor activity in real time (PST
pins). A four-bit wide debug data bus (DDATA) displays operand data and change-of-flow addresses,
which helps track the machine’s dynamic execution path.
1.2.24
Crystal and On-Chip PLL
Typically, an external 16.92 MHz or 33.86 MHz clock input is used for CD R/W applications, while an
11.2896 MHz clock is more practical for Portable CD player applications. However, the on-chip
programmable PLL, which generates the processor clock, allows the use of almost any low frequency
external clock (5-35 MHz).
Two clock outputs (MCLK1 and MCLK2) are provided for use as Audio Master Clock. The output
frequencies of both outputs are programmable to Fxtal, Fxtal/2, Fxtal/3, and Fxtal/4. The Fxtal/3 option is
only available when the 33.86 MHz crystal is connected.
The SCF5250 supports VCO operation of the oscillator by means of a 16-bit pulse density modulation
output. Using this mode, it is possible to lock the oscillator to the frequency of an incoming IEC958 or IIS
signal. The maximum trim depends on the type and design of the oscillator. Typically a trim of +/- 100 ppm
can be achieved with a crystal oscillator and over +/- 1000 ppm with an LC oscillator.
1.2.25
Boot ROM
The boot ROM on the SCF5250 serves to boot the CPU in designs which do not have external Flash
memory or ROM. Typically this occurs in systems which have a separate MCU to control the system,
and/or the SCF5250 is used as a stand-alone decoder.
The SCF5250 can be booted in one of three modes:
External ROM
Internal ROM Master mode – boots from I2C, SPI, or IDE
Internal ROM Slave mode – boots from I2C or UART
1.2.26
Voltage Regulator
The SCF5250 contains an on-chip linear regulator that generates 1.2V from a 3.3V input. The regulator is
self-contained and drives the 1.2V core voltage out on one pin that can be used to power the core supply
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