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參數(shù)資料
| 型號(hào)： | SCM6343YJ12AR |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 15 Bit 3.3 V Asynchronous Fast Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | 0.400 INCH, SOJ-44 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大小： | 169K |
| 代理商： | SCM6343YJ12AR |
MCM6343
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V
±
0.3 V, TA = 0 to + 70
°
C, Unless Otherwise Noted)
(TA = – 40 to + 85
°
C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level
Logic Input Pulse Levels
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.50 V
0 to 3.0 V
. . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.50 V
. . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1
READ CYCLE TIMING
(See Notes 1, 2, and 3)
Parameter
Symbol
b l
MCM6343–12
MCM6343–15
U i
Unit
Notes
Min
Max
Min
Max
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
tBLQV
tBLQX
tBHQZ
12
—
15
—
ns
4
Address Access Time
—
12
—
15
ns
Enable Access Time
—
12
—
15
ns
5
Output Enable Access Time
—
6
—
7
ns
Output Hold from Address Change
3
—
3
—
ns
Enable Low to Output Active
3
—
3
—
ns
6, 7, 8
Output Enable Low to Output Active
0
—
0
—
ns
6, 7, 8
Enable High to Output High–Z
0
6
0
7
ns
6, 7, 8
Output Enable High to Output High–Z
0
6
0
7
ns
6, 7, 8
Byte Enable Access Time
—
6
—
7
ns
Byte Enable Low to Output Active
0
—
0
—
ns
6, 7, 8
Byte High to Output High–Z
0
6
0
7
ns
6, 7, 8
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. Device is continuously selected (E
≤
VIL, G
≤
VIL).
4. All read cycle timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, tEHQZ max
tELQX min, and tGHQZ max
to device.
7. This parameter is sampled and not 100% tested.
8. Transition is measured
±
200 mV from steady–state voltage.
tGLQX min, both for a given device and from device
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a minimum
since the system must supply at least that much time.
On the other hand, responses from the memory are
specified from the device point of view. Thus, the ac-
cess time is shown as a maximum since the device
never provides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
Figure 1. AC Test Load
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