參數(shù)資料
型號(hào)： SCM69C233
廠(chǎng)商： Motorola, Inc.
英文描述： 4K x 64 Content Addressable Memory(4K x 64內(nèi)容可尋址存儲(chǔ)器)
中文描述： 4K的× 64內(nèi)容可尋址存儲(chǔ)器（4K的× 64內(nèi)容可尋址存儲(chǔ)器）
文件頁(yè)數(shù)： 1/22頁(yè)
文件大?。?/td> 167K
代理商： SCM69C233
MCM69C233
SCM69C233
1
MOTOROLA FAST SRAM
Motorola, Inc. 2000
4K x 64 CAM
The MCM69C233 is a flexible content–addressable memory (CAM) that can
contain 4096 entries of 64 bits each. The widths of the match field and the output
field are programmable, and the match time is designed to be 210 ns. As a result,
the MCM69C233 is well suited for datacom applications such as Virtual Path
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup
in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C233 is
user defined, with a trade–off between the time between matches and the rate
of new entries added to the CAM.
4096 Entries
210 ns Match Time
Mask Register to “Don’t Care” Selected Bits
Depth Expansion by Cascading Multiple Devices
66 MHz Maximum Clock Rate
Programmable Match and Output Field Widths
Concurrent Matching of Virtual Path Circuits and Virtual Connection
Circuits in ATM Mode
Separate Ports for Control and Match Operations
300 ns Insertion Time if 1 of 12 Entry Queue Locations is Empty
18 ms Initialization Time After Fast Insertion (at Power–Up Only)
Single 3.3 V
±
5% Supply
IEEE Standard 1149.1 Test Port (JTAG)
100–Pin TQFP Package
Related Products
— MCM69D536, MCM69D618 (Dual I/O, Dual Address RAMs)
— MCM67Q709A, MCM67Q909 (Separate I/O RAMs)
— MCM69C432, MCM69C232, MCM69C433 (CAMs)
CONTROL PORT
A2 – A0
DQ15 – DQ0
SEL
WE
IRQ
DTACK
12 x 64
ENTRY QUEUE
STATUS/
CONTROL
LOGIC
INPUT REG
4K x 64
CAM
TABLE
MATCH PORT
MQ31 – MQ0
K
G
LH/SM
LL
MC
MS
VPC
RESET
KMODE
Order this document
by MCM69C233/D
SEMICONDUCTOR TECHNICAL DATA
MCM69C233
SCM69C233
TQ PACKAGE
TQFP
CASE 983A–01
REV 2
6/19/00
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