參數(shù)資料
型號(hào)： SCM69C232
廠商： Motorola, Inc.
英文描述： 4Kx64 Content Adressable Memory(4Kx64內(nèi)容可尋址存儲(chǔ)器)
中文描述： 4Kx64內(nèi)容可尋址存儲(chǔ)器（4Kx64內(nèi)容可尋址存儲(chǔ)器）
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 159K
代理商： SCM69C232
MCM69C232
SCM69C232
7
MOTOROLA FAST SRAM
FUNCTIONAL DESCRIPTION
The MCM69C232 is a flexible CAM that can contain 4096
entries of 64 bits each. The widths of the match field and the
output field are programmable, and the match time is de-
signed to be 160 ns. As a result, the MCM69C232 is well
suited for datacom applications such as VPI/VCI translation
in ATM switches up to OC12 (622 Mbps) data rates and MAC
address lookup in Ethernet/Fast Ethernet bridges. The
match duty cycle of the MCM69C232 is determined by the
user, with a trade–off between the match cycle time and the
rate of entries added to/deleted from the CAM. With the mini-
mum required 40 ns of idle time between matches, a typical
value of 2440 insertions or deletions per second can be
made. See Figure 3 for a graph of the relationship between
insertion/deletion pairs and match cycle time.
In its basic operating mode, the MCM69C232 reads a data
input word through the MQ bus and compares it to all the
entries in its CAM table. The MC pin is always asserted after
the comparisons have been made. If a match is found, the
MS pin is asserted, and the data associated with the match-
ing entry is output on the MQ bus. If no match is found, the
MQ bus remains in a high–impedance state to facilitate
depth expansion via the cascading of multiple CAMs.
Before the basic operating mode can be entered, several
start–up functions must be performed. First, the output width
and match width must be designated by setting the global–
mask register. Second, a choice must be made between
buffered–entry mode and fast–entry mode. Next, the match/
output data pairs must be loaded into the table. Depending
on the entry mode of choice, the table may have to be initial-
ized. Optionally, the “almost–full” point may be set to provide
warning of impending table overflow.
The input bits to be compared are defined by the global–
mask register. The mask bits that are 0 correspond to the bits
that are used in the match operation.Typically, the bits that
are used in matching are the high order bits in the 64–bit
CAM table entries, and the bits that are used as outputs are
the low order bits. While any of the bits can be defined as
match bits, the low order 32 bits of an entry are always driven
on the MQ bus as output data.
The choice of entry mode is a trade–off between speed of
entry and latency before matching operations can begin. In a
typical application, the fast–entry mode will be used to load
the initial values into the CAM table. Subsequently, the initial-
ize–table operation, which takes 12 ms, must be executed to
establish the required linkages and relationships among the
entries. After match operations have begun, the buffered–
entry mode should be used to enter new values dynamically;
even one addition in fast–entry mode will disable matching
until the table is reinitialized. Table insertions using the buff-
ered–entry mode and the fast–entry mode actually take the
same amount of time unless the entry queue is full. The
capacity of the queue is 12 entries.
After the entry mode choice is made, the table can be
loaded. Each 64–bit entry is constructed by writing a 16–bit
value to each of the 4 I/O registers in the MCM69C232. The
insertion can then be processed. After all the start–up entries
have been loaded into the CAM table, the initialization opera-
tion is run if required. Normal matching operations can then
begin. A delete operation is provided to remove stale data
from the CAM table.
Several error codes are defined in the details of the
instruction set. When an error occurs, its corresponding code
is written into the error register and the error bit in the flag
register is set. The error bit is cleared and the error register is
set to FFFF16 by the next write to the operation register.
PROGRAMMING MODEL
Three types of registers are accessible through the
MCM69C232 control port: I/O registers, an operation regis-
ter, and result/condition code registers. Each register is 16
bits in length.
ADDRESS
OFFSET
REGISTER NAME
BIT NUMBER
I/O REGISTER 0
0
I/O REGISTER 1
1
I/O REGISTER 2
2
I/O REGISTER 3
3
OPERATION REGISTER
4
FLAG REGISTER
5
ERROR CODE REGISTER
6
INTERRUPT REGISTER
7
15
0
FLAG BIT DEFINITIONS
Bit 0: 1 = At least one interrupt enabled,
0 = No interrupts generated
Bit 1:
1 = Last control port match successful,
0 = Last match unsuccessful
Bit 2: 1 = Table initialized, 0 = Table not initialized
Bit 3:
1 = buffered–entry mode, 0 = fast–entry mode
Bit 4:
1 = Entry queue empty,
0 = Entry queue not empty
Bit 5:
1 = Entry queue full, 0 = Entry queue not full
Bit 6:
1 = CAM table full, 0 = CAM table not full
Bit 7:
1 = Error condition set, 0 = No error
Bit 8:
1 = Table almost full, 0 = Table not almost full
Bit 9:
1 = ATM mode, 0 = Standard mode
Bit 10: 1 = Last operation complete, 0 = Not yet complete
ERROR CODES
FFFF
FFFD
FFFC
FFFB
FFFA
FFF9
FFF8
No error
Invalid instruction
Queue not empty for read
Table not initialized
Queue not empty for write
CAM table full
Entry queue full
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