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參數(shù)資料
| 型號： | SCM69C432 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16K x 64Content Addressable Memory(16K x 64內(nèi)容可尋址存儲器) |
| 中文描述： | 16K的x 64Content尋址存儲器（16K的× 64內(nèi)容可尋址存儲器） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 160K |
| 代理商： | SCM69C432 |
MCM69C432
SCM69C432
8
MOTOROLA FAST SRAM
INTERRUPT BIT DEFINITIONS
Bit 0:
1 = Enable interrupt on insert with full entry
queue
1 = Enable interrupt on insert with full table
1 = Enable interrupt on completion of
CHECK–FOR–VALUE instruction
1 = Enable interrupt on completion of
INITIALIZE–TABLE instruction
1 = Enable interrupt on failed attempt to enter
fast–entry mode
1 = Enable interrupt on CAM table reaching
almost–full point
1 = Enable interrupt on fast read with non–empty
queue
1 = Enable interrupt on illegal instruction
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
INSTRUCTION SET DETAILS
The MCM69C432 is prepared for match operations by
writing to data and instruction registers via the control port. In
the general case, required data is loaded into I/O registers
0 – 3, then an instruction is issued by writing an operation
code to the instruction register. As a result of running an
instruction, the CAM table can be modified, bit(s) can be set
in the flag register, error codes can be returned in the error
code register, and an interrupt can be generated if enabled.
For a particular condition to generate an interrupt, the inter-
rupt register bit specific to that condition must be set. The
user should verify that the operation–complete bit of the flag
register is set before executing the next instruction, if the
instruction just executed modifies I/O registers.
Table 1. MCM69C432 Operation Summary
Operation
Description
OP Code (Base 16)
INSERT VALUE
Loads a new entry into the CAM table
0000 or 000F
DELETE VALUE
Removes an entry from the CAM table
0001 or 000E
CHECK FOR VALUE
Runs a match cycle via the control port
0006
INITIALIZE TABLE
Prepares CAM table for matching
000B
FAST–ENTRY MODE
Selects entry mode suited for initial CAM table load
0004
BUFFERED–ENTRY MODE
Selects entry mode suited for simultaneous loading
and matching
0005
SET ATM MODE
Enter mode that provides concurrent VPC/VCC
search
0008
RETURN ENTRY COUNT
Determines number of entries in CAM
0003
SET GLOBAL–MASK REGISTER
Determines match bits to be checked in a match
operation
0002 or 000D
SET ALMOST–FULL POINT
Defines CAM almost–full condition
0007
SET FAST–READ REGISTER
Defines table entry that is output by the fast–read
operation
0009
FAST READ
Outputs one CAM table entry
000A
INSERT VALUE
This instruction is used to load a new match/output value
into the CAM. The contents of I/O registers 0 – 3 are con-
catenated, with bit 15 of register 3 as the most significant bit,
and bit 0 of register 0 as the least significant bit.
If the MCM69C432 is running in the buffered–entry mode,
the resulting 64–bit value is written to the first available loca-
tion in the entry queue, and is immediately available for
matching. If a buffered insert–value instruction is attempted
when the entry queue is full (indicated by bit 5 of the flag reg-
ister = 1), no value is written, an error code of FFF816 is re-
turned in the error code register, and the error–condition flag
(bit 7) is set in the flag register. An interrupt is generated, if
enabled by bit 0 of the interrupt register being set.
If the MCM69C432 is running in the fast–entry mode, the
concatenated 64–bit value is written directly to the CAM
array. If an insert–value instruction is attempted when in
fast–entry mode and the table is full, no value is written, an
error code of FFF916 is returned in the error code register,
and the error–condition flag (bit 7) is set in the flag register.
(The table–full condition is indicated by bit 6 of the flag regis-
ter being set.) An interrupt is generated, if enabled by bit 1 of
the interrupt register being set.
Only one entry is allowed for a given match pattern. If an
entry is made in the table that duplicates an existing match
pattern, it will overwrite the entry already in the CAM table, if
the CAM is in buffered–entry mode. The user must ensure
that no entries with the same match pattern are inserted in
fast–entry mode.
DELETE VALUE
This instruction is used to remove a match/output value
from the CAM. The contents of I/O registers 0 – 3 are con-
catenated, with bit 15 of register 3 as the most significant bit,
and bit 0 of register 0 as the least significant bit. The bits that
have a 0 in the corresponding bit of the global–mask register
are used to find a matching entry in the CAM table. If such an
entry is found, it is invalidated. Note that any bit that is not a
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