參數(shù)資料
型號: SCN2652AC2A44
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: NT Series Toggle Switch, 1 pole, 3 position, Solder terminal, Locking Lever
中文描述: 1 CHANNEL(S), 2M bps, MULTI PROTOCOL CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 16/28頁
文件大?。?/td> 651K
代理商: SCN2652AC2A44
Philips Semiconductors
Product specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
1995 May 01
16
Table 8. Receiver Data/Status Register (RDSR)–(Read Only)
BIT
00–07
NAME
RxDB
MODE
BOP/BCP
FUNCTION
Receiver data buffer. Contains assembled characters from the RxSR. If VRC is specified, the
parity bit is stripped.
Receiver start of message = 1 when a FLAG followed by a non-FLAG has been received and
the latter character matches the secondary station if SAM = 1. RxA will be asserted when
RSOM = 1. RSOM resets itself after one character time and has no affect on RxSA.
08
RSOM
BOP
09
REOM
BOP
Receiver end of message = 1 when the closing FLAG is detected and the last data character
is loaded into RxDB or when an ABORT/GA character is received. REOM is cleared on
reading RDSR
H
, reset operation, or dropping of RxE.
Received ABORT or GA character = 1 when the receiver senses an ABORT character if
SS/GA = 0 or a GA character if SS/GA = 1. RAB/GA is cleared on reading RDSR
H
, reset
operation, or dropping of RxE. A received abort does not set RxDA.
10
RAB/GA
BOP
11
ROR
BOP/BCP
Receiver overrun = 1 indicates the processor has not read last character in the RxDB within
one character time + 1/2 RxC period after RxDA is asserted. Subsequent characters will be
lost. ROR is cleared on reading RDSR
H
, reset operation, or dropping of RxE.
Assembled bit count. Specifies the number of bits in the last received data character of a
message and should be examined by the processor when REOM = 1(RxDA and RxSA
asserted). ABC = 0 indicates the message was terminated (by a flag or GA) on a character
boundary as specified by PCR
8–10
. Otherwise, ABC = number of bits in the last data
character. ABC is cleared when RDSR
is read, reset operation, or dropping RxE. The
residual character is right justified inRDSR
L
.
Receiver error indicator should be examined by the processor when REOm = 1 in BOP, or
when the processor determines the last data character of the message in BCP with CRC or
when RxSA is set in BCP with VRC.
CRC–CCITT preset to 1’s/0’s as specified by PCSAR
8–10
:
RERR = 1 indicates FCS error (CRC
F0B8 or
0)
RERR = 0 indicates FCS received correctly (CRC = F0B8 or = 0)
CRC–16 preset to 0’s on 8-bit characters specified by PSCAR
8–10
:
RERR = 1 indicates CRC–16 received correctly (CRC = 0).
RERR = 0 indicates CRC–16 error (CRC
0)
VRC specified by PCSAR
:
RERR = 1 indicates VRC error
RERR = 0 indicates VRC is correct.
12–14
ABC
BOP
15
RERR
BOP/BCP
DC ELECTRICAL CHARACTERISTICS
1, 2
PARAMETER
TEST CONDITIONS
LIMITS
Typ
UNIT
Min
Max
Input voltage
V
IL
V
IH
Output voltage
V
OL
V
OH
I
CC
Leakage current
I
IL
I
OL
Capacitance
C
IN
C
OUT
Low
High
0.8
V
2.0
Low
High
I
OL
= 1.6mA
I
OH
= –100
μ
A
V
CC
= 5.25V, T
A
= 0
°
C
0.4
V
2.4
Power supply current
150
mA
Input
Output
V
IN
= 0 to 5.25V
V
OUT
= 0 to 5.25V
10
10
μ
A
Input
Output
V
IN
= 0V, f = 1MHz
V
OUT
= 0V, f = 1MHz
20
20
pF
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