參數(shù)資料
型號: SCN26562C4A52
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual universal serial communications controller DUSCC
中文描述: 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 2/17頁
文件大?。?/td> 101K
代理商: SCN26562C4A52
Philips Semiconductors
Product specification
SCN26562
Dual universal serial communications controller (DUSCC)
1995 May 1
2
Character-Oriented Protocol Features
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
LRC or CRC generation and checking
Optional opening PAD transmission
One or two SYN characters
External sync capability
SYN detection and optional stripping
SYN or MARK line-fill on underrun
Idle in MARK or SYNs
Parity, FCS, overrun, and underrun error detection
BISYNC Features
EBCDIC or ASCII header, text and control messages
SYN, DLE stripping
EOM (end of message) detection and transmission
Auto transparent mode switching
Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
Character length: 5 to 8 bits
Detection and transmission of residual character: 0–7 bits
Automatic switch to programmed character length for I field
Zero insertion and detection
Optional opening PAD transmission
Detection and generation of FLAG, ABORT, and IDLE bit patterns
Detection and generation of shared (single) FLAG between
frames
Detection of overlapping (shared zero) FLAGs
ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun
Idle in MARK or FLAGs
Secondary address recognition including group and global
address
Single- or dual-octet secondary address
Extended address and control fields
Short frame rejection for receiver
Detection and notification of received end of message
CRC generation and checking
SDLC loop mode capability
ORDERING INFORMATION
DESCRIPTION
V
CC
= +5V +5%, T
A
= 0
°
C to +70
°
C
Serial Data Rate =
4Mbps Maximum
SCN26562C4N48
DWG #
48-Pin Plastic Dual In-Line Package (DIP)
SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package
SCN26562C4A52
SOT238-3
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
T
A
Operating ambient temperature
2
T
STG
Storage temperature
V
CC
Voltage from V
CC
to GND
3
V
S
Voltage from any pin to ground
3
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150
°
C maximum junction temperature and thermal
resistance of 36
°
C/W junction to ambient for ceramic DIP, 40
°
C/W for plastic DIP, and 42
°
C/W for PLCC.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
PARAMETER
RATING
0 to +70
-65 to +150
–0.5 to +7.0
–0.5 to V
CC
+0.5
UNIT
°
C
°
C
V
V
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