- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372130 > SCN2681AC1A44 (NXP SEMICONDUCTORS) RB Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 3.3V; Power: 1W; Low Cost 1W Converter; Power Sharing on Dual Output Version; Industry Standard Pinout; 1kVDC & 2kVDC Isolation Options; Optional Continuous Short Circuit Protected; UL94V-0 Package Material; Efficiency to 85% PDF資料下載
參數(shù)資料
| 型號： | SCN2681AC1A44 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RB Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 3.3V; Power: 1W; Low Cost 1W Converter; Power Sharing on Dual Output Version; Industry Standard Pinout; 1kVDC & 2kVDC Isolation Options; Optional Continuous Short Circuit Protected; UL94V-0 Package Material; Efficiency to 85% |
| 中文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MO-047AC, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 205K |
| 代理商： | SCN2681AC1A44 |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
7
BLOCK DIAGRAM
8
D0–D7
RDN
WRN
CEN
A0–A3
RESET
INTRN
X1/CLK
X2
4
BUS BUFFER
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTERRUPT CONTROL
IMR
ISR
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
CTIMER
XTAL OSC
CSRA
CSRB
ACR
CTUR
CTLR
CHANNEL A
TRANSMIT
HOLDING REG
SHTRANSMIT
HORECEIVE
SHIRECEIVE
MRA1, 2
CRA
SRA
INPUT PORT
CHANGE OF
DETSTATE
OUTPUT PORT
SFUNCTION
OPCR
TxDA
RxDA
IP0-IP6
OP0-OP7
V
CC
GND
C
T
I
CHANNEL B
(AS ABOVE)
IPCR
ACR
OPR
RxDB
TxDB
8
7
SD00085
Figure 2. Block Diagram
BLOCK DIAGRAM
The SCN2681 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port.
Refer to the block diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer.
Interrupt Control
A single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
相關PDF資料 |
PDF描述 |
|---|---|
| SCN2681 | Dual asynchronous receiver/transmitter DUART |
| SCN2681AE1N24 | Dual asynchronous receiver/transmitter DUART |
| SCN2681AE1N28 | CCTV VIDEO BALUN |
| SCN2681AE1N40 | Dual asynchronous receiver/transmitter DUART |
| SCN2681AC1N24 | Dual asynchronous receiver/transmitter DUART |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCN2681AC1F40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| SCN2681AC1N24 | 制造商:STMicroelectronics 功能描述:UART, 24 Pin, Plastic, DIP |
| SCN2681AC1N28 | 制造商:NXP Semiconductors 功能描述: |
| SCN2681AC1N40 | 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:UART, 40 Pin, Plastic, DIP |
| SCN2681AE1A44 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual asynchronous receiver/transmitter DUART |
發(fā)布緊急采購，3分鐘左右您將得到回復。