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參數(shù)資料
| 型號： | SCN68652AC2A44 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Multi-protocol communications controller MPCC |
| 中文描述： | 1 CHANNEL(S), 2M bps, MULTI PROTOCOL CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 651K |
| 代理商： | SCN68652AC2A44 |
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Philips Semiconductors
Product specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
2
1995 May 01
853-1068 15179
DESCRIPTION
The SCN2652/68652 Multi-Protocol Communications Controller
(MPCC) is a monolithic n-channel MOS LSI circuit that formats,
transmits and receives synchronous serial data while supporting
bit-oriented or byte control protocols. The chip is TTL compatible,
operates from a single +5V supply, and can interface to a processor
with an 8 or 16-bit bidirectional data bus.
APPLICATIONS
Intelligent terminals
Line controllers
Network processors
Front end communications
Remote data concentrators
Communication test equipment
Computer to computer links
FEATURES
DC to 2Mbps data rate
Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC
Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)
Programmable operation
–
8 or 16-bit tri-state data bus
–
Error control – CRC or VRC or none
–
Character length – 1 to 8 bits for BOP or 5 to 8 bits for BCP
–
SYNC or secondary station address comparison for BCP-BOP
–
Idle transmission of SYNC/FLAG or MARK for BCP-BOP
Automatic detection and generation of special BOP control
sequences, i.e., FLAG, ABORT, GA
Zero insertion and deletion for BOP
Short character detection for last BOP data character
SYNC generation, detection, and stripping for BCP
Maintenance mode for self-testing
TTL compatible
Single +5V supply
PIN CONFIGURATION
Pin Function
Pin Function
1
NC
2
CE
3
RxC
4
RxSI
5
S/F
6
RxA
7
RxDA
8
RxSA
9
RxE
10 GND
11
DB08
12 NC
13 DB09
14 DB10
15 DB11
16 DB12
17 DB13
18 DB14
19 DB15
20 R/W
21 A2
22 A1
23 NC
24 A0
25 BYTE
26 DBEN
27 DB07
28 DB06
29 DB05
30 DB04
31 DB03
32 DB02
33 DB01
34 NC
35 DB00
36 V
37 RESET
38 TxA
39 TxBE
40 TxU
41 TxE
42 TxSQ
43 TxC
44 MM
1
39
17
28
40
29
18
7
PLCC
6
TOP VIEW
INDEX
CORNER
NOTE: DB00 is least significant bit, highest number
(that is, DB15, A2) is most significant bit.
24
23
22
21
20
19
18
17
16
15
28
27
12
10
11
9
8
7
6
5
4
3
2
1
14
13
26
25
29
30
31
32
33
34
35
36
37
38
39
40
CE
RxC
RxSI
S/F
RxA
RxDA
RxSA
RxE
GND
DB08
DB09
DB10
DB11
DB12
DB13
DB14
DB15
R/W
A2
A1
A0
BYTE
DBEN
DB07
DB06
DB05
DB04
DB03
DB02
DB01
DB00
V
CC
RESET
TxA
TxBE
TxU
TxE
TxSQ
TxC
MM
DIP
TOP VIEW
SD00057
Figure 1. Pin Configuration
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