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參數(shù)資料
| 型號： | SCN68681E1A44 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual asynchronous receiver/transmitter DUART |
| 中文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-018, LCC-44 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 187K |
| 代理商： | SCN68681E1A44 |
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Philips Semiconductors
Product specification
SCN68681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
7
AC CHARACTERISTICS
T
A
= -40
°
C to +85
°
C,
V
CC
= 5.0V
±
10%
1, 2, 3, 4
SYMBOL
PARAMETER
LIMITS
Typ
3
UNIT
Min
Max
Reset Timing (See Figure 3)
t
RES
RESETN pulse width
Bus Timing
(See Figures 4, 5, 6)
t
AS
A1-A4 setup time to CSN Low
t
AH
A1-A4 hold time from CSN Low
t
RWS
RWN setup time to CSN High
t
RWH
RWN holdup time to CSN High
t
CSN High pulse width
t
CSW
CSN or IACKN High from DTACKN Low
t
DD
Data valid from CSN or IACKN Low
t
DF
Data bus floating from CSN or IACKN High
7
t
DS
Data setup time to CLK High
t
DH
Data hold time from CSN High
t
DAL
DTACKN Low from read data valid
t
DCR
DTACKN Low (read cycle) from CLK High
t
DCW
DTACKN Low (write cycle) from CLK High
t
DAH
DTACKN High from CSN or IACKN High
t
DTACKN High impedance from CSN or IACKN High
t
DAT
CSN or IACKN setup time to clock High
Port Timing (See Figure 7)
t
PS
Port input setup time to CSN Low
t
PH
Port input hold time from CSN High
t
PD
Port output valid from CSN High
Interrupt Reset Timing (See Figure 8)
INTRN or OP3-OP7 when used as interrupts negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
t
Reset command (delta break interrupt)
IR
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
Clock Timing (See Figure 9)
t
X1/CLK High or Low time
f
CLK
X1/CLK frequency
t
CTC
CTCLK High or Low time
f
CTC
CTCLK frequency
t
RX
RxC High or Low time
f
RX
RxC frequency (16X)
(1X)
t
TX
TxC High or Low time
f
TX
TxC frequency (16X)
(1X)
Transmitter Timing (See Figure 10)
t
TXD
TxD output delay from TxC external clock input on IP pin
t
TCS
Output delay from TxC low at OP pin to TxD data output
Receiver Timing (See Figure 11)
t
RXS
RxD data setup time before RxC high at external clock input on IP pin
t
RXH
RxD data hold time after RxC high at external clock input on IP pin
NOTES:
1. Parameters are valid over specified temp. range. See Ordering information table for applicable operating temp. and V
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with
a transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input
voltages of 0.8V and 2.0V as appropriate.
3. Typical values are at +25
°
C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C
= 150pF, except interrupt outputs. Test condition for interrupt outputs: C
= 50pF, R
= 2.7k
to V
.
5. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus reads are not performed.
Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
6. This specification imposes a lower bound on CSN and IACKN Low, guaranteeing that it will be Low for at least 1 CLK period. This
requirement is made on CSN only to insure assertion of DTACKN and not to guarantee operation of the part.
7. This spec is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as shown in the timing diagram,
not to guarantee operation of the part. If setup time is violated, DTACKN may be asserted as shown, or may be asserted 1 clock cycle later.
8. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz.
200
ns
10
100
0
0
90
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
175
100
100
20
0
125
125
100
125
90
0
0
ns
ns
ns
400
300
300
300
300
300
300
ns
ns
ns
ns
ns
ns
100
0
100
0
220
0
0
220
0
0
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
3.6864
4.0
4.0
2.0
1.0
2.0
1.0
350
150
ns
ns
240
200
ns
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SCN68681E1F40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual asynchronous receiver/transmitter DUART |
| SCN68681E1N40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual asynchronous receiver/transmitter DUART |
| SCN-800 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:800W Single Output With Parallel Function |
| SCN-800-12 | 制造商:ASTRODYNE 制造商全稱:Astrodyne Corporation 功能描述:800W With Parallel Function |
| SCN-800-15 | 制造商:ASTRODYNE 制造商全稱:Astrodyne Corporation 功能描述:800W With Parallel Function |
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