參數(shù)資料
型號(hào): sda 9205
廠商: SIEMENS AG
英文描述: Triple 8-Bit Analog-to-Digital-Converter(三倍8位A/D轉(zhuǎn)換器)
中文描述: 三8位模擬到數(shù)字轉(zhuǎn)換器(三倍8位的A / D轉(zhuǎn)換器)
文件頁(yè)數(shù): 3/31頁(yè)
文件大?。?/td> 560K
代理商: SDA 9205
SDA 9205-2
Semiconductor Group
3
Pin Definitions and Functions
Pin No.
Symbol
Function
63 to 2
C7 to C0
V
QGNDC
UFLC
Digital outputs of ADC C (port C) C0 least significant bit
3
Output stages supply ground of port C
4
Underflow data output of ADC C
5
OFLC
Overflow data output of ADC C
6
OENC
Output enable of port C
7
DTC
Binary/two’s complement output port C
8/9/11/17
CONT3-
CONT0
V
REFHC
V
CCC
V
AGNDC
V
REFLC
AINC
V
REFHB
V
CCB
V
AGNDB
V
REFLB
AINB
V
REFHA
V
CCA
V
AGNDA
AINA
V
REFLA
TEST
Control inputs for different digital output multiplex formats –
refer to logic table
10
Reference voltage high of ADC C (+ 2.5 V)
12
Analog positive supply voltage of ADC C (+5 V)
13
Analog ground of ADC C
14
Reference voltage low of ADC C (+ 5 V)
15
Analog voltage input of ADC C
16
Reference voltage high of ADC B (+ 2.5 V)
18
Analog positive supply voltage of ADC B (+ 5 V)
19
Analog ground of ADC B
20
Reference voltage low of ADC B (+ 0.5 V)
21
Analog voltage input of ADC B
22
Reference voltage high of ADC A (+ 2.5 V)
23
Analog positive supply voltage of ADC A (+ 5 V)
24
Analog ground of ADC A
25
Analog voltage input of ADC A
26
Reference voltage low of ADC A (+ 0.5 V)
27/29
Factory use only, connect to 0 V
28
DTA
Binary/two’s complement output of port A
30
CLAMP
Clamp input for all three channels
31
UFLA
Underflow data output of ADC A
32
OFLA
V
QGNDA
A7 to A0
Overflow data output of ADC A
33
Output stages supply ground of port A
34 to 41
Digital outputs of ADC A (port A) A0 least significant bit
42
OENA
V
DDQA
Output enable of port A
43
Output stages supply voltage of port A
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