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參數(shù)資料
| 型號： | SDC-19204-304 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP40 |
| 封裝： | 1.140 X 2.020 INCH, 0.230 INCH HEIGHT, TDIP-40 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 124K |
| 代理商： | SDC-19204-304 |
4
QUADRATURE VOLTAGES. In a synchro, quadrature voltages
are, by definition, the resulting 90° fundamental signal in the
nulled out error voltage (e) in the converter. A digital position
error will result due to the interaction of this quadrature voltage
and a reference phase shift between the converter signal and
reference inputs. The magnitude of this error is given by the fol-
lowing formula:
Magnitude of Error = (Quadrature Voltage/F.S. signal) tan(α)
Where:
Magnitude of Error is in radians.
Quadrature Voltage is in volts.
Full-Scale signal is in volts.
α = signal to REF phase shift.
An example of the magnitude of error is as follows:
Let: Quadrature Voltage = 11.8 mV
Let: F.S. signal = 11.8 V
Let: a = 6°
Then: Magnitude of Error = 0.35 min
≈ 1 LSB
in the 16th bit.
Note: Quadrature is composed of static quadrature which is
specified by the resolver supplier plus the speed voltage which is
determined by the following formula:
Speed Voltage = (rotational speed/carrier freq) F.S. signal
Where :
Speed Voltage is the quadrature due to rotation.
Rotational speed is the RPS (rotations per second)
of the synchro.
Carrier frequency is the REF in Hz.
ANALOG CONDITIONER
The Analog Conditioner section performs three functions. It con-
verts analog ground from 5.5 V to 0 V, provides a gain of 2 for AC
Error (e) and a gain of 2.2 for Velocity (VEL). The velocity scaling
sensitivity can be increased with an external resistor. Refer to
VELOCITY PROGRAMMING section for more information.
POWER SUPPLY CONDITIONER
The power supply conditioner lowers the internal power supply
voltage to the custom CMOS chip to +11 V from the +15 V sup-
ply. The +11 V will track the +15 V. Internal analog ground is one
half of +11 V or +5.5 V, nom.
INTERNAL DC REFERENCE VOLTAGE (V). This internal volt-
age is not required externally for normal operation of the con-
verter. It is used as the internal DC reference common with the
direct input option. It is nominally +5.5 V and is proportional to
the +15 VDC supply.
DIGITAL INTERFACE
The digital interface circuitry performs three main functions:
1. Latches the output bits during an Inhibit (INH) command,
allowing stable data to be read.
2. Furnishes parallel tri-state data formats.
3. Acts as a buffer between the internal CMOS logic and the
external TTL logic.
By applying an Inhibit (INH) command to the SDC-19204/6 the
data will lock in the output transparent latch without interfering
with the continuous tracking of the converter’s feedback loop.
Therefore, the digital angle
φ is always updated, and the INH can
be applied for an arbitrary amount of time. The Inhibit
Transparent Latch and the 50 ns delay are part of the inhibit cir-
cuitry. For further information, see the INHIBIT (INH, pin 9) para-
graph. The BIT detect circuitry monitors the error level (D) from
the demodulator and the LOS (loss of signal) detector detects
disconnected resolver inputs.
LOGIC INPUT/OUTPUT
The digital angle outputs are buffered and provided in a two-byte
format. The first byte contains the MSBs (bits 1-8) and is enabled
by placing EM (pin 10) to a logic 0. Depending on the user pro-
grammed resolution, the second byte contains the LSBs and is
enabled by placing EL (pin 11) to a logic 0. The second byte will
contain either bits 9-10 (10-bit resolution), bits 9-12 (12-bit reso-
lution), bits 9-14 (14-bit resolution) or bits 9-16 (16-bit resolu-
tion). All unused LSBs will be at logic 0. TABLE 2 lists the angu-
lar weight for the digital angle outputs.
The digital angle outputs are valid 150 ns after EM or EL is acti-
vated with a logic 0, and are high impedance within 100 ns, max,
after EL and EM are set to logic 1. Both enables are internally
pulled up to +5 V by -10
A max current sources.
DIGITAL ANGLE OUTPUT TIMING
The digital angle output is 10, 12, 14, or 16 parallel data bits. All
logic outputs are short-circuit proof to ground and +5 V. The CB
(Converter Busy) output is a positive, 0.4 to 0.7 s pulse.
V
10k
Va
100k
40
C
REF
SDC-19204/6
Note: Choose C such that the Va-to-REF phase lead is equal to the
synchro-to-REF phase lead plus 9
s.
FIGURE 3. PHASE SHIFTING THE REF INPUT
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