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參數(shù)資料
| 型號(hào)： | SDC-19204-304 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP40 |
| 封裝： | 1.140 X 2.020 INCH, 0.230 INCH HEIGHT, TDIP-40 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | SDC-19204-304 |
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11
SDC-19204 APPLICATIONS
USING THE SDC-19204/6 IN THE CT MODE
The CT mode can be applied in servo systems, as shown in FIG-
URE 18. In this application changes in position are commanded
by the computer through signals fed to the CT. The CT then dri-
ves the motors through DC power amplifiers.
MULTITURN APPLICATIONS-USE OF MAJOR CARRY (MC,
PIN 32)
Refer to Major Carry paragraph for details.
USING THE SDC-19204/6 AS AN S/D WITH VEL TO
STABILIZE POSITION LOOP
FIGURE 19 illustrates a typical use of a SDC-19204/6 connect-
ed as an S/D using the VEL output to stabilize the position loop.
AMP
DEMODULATOR
COMPUTER
SDC-19204/6 as a CT
REF
SYNCHRO
e
S
FIGURE 18. CT MODE APPLICATION
AMP
COMPUTER
S/D
CON-
VERTER
REF
SOURCE
SYNCHRO
D/A
VEL
FIGURE 19. S/D WITH VEL TO STABILIZE POSITION
INTERFACING THE SDC-19204/6
WITH AN IBM PC/XT/AT
The SDC-19204/6 can be connected to an IBM PC/XT/AT
through the IBM PC Bus located at address HEX 300 through
303. This location is reserved by the PC for prototype cards.
FIGURE 21 illustrates the connection to the IBM PC Bus; FIG-
URE 20 illustrates the timing considerations for the interface.
SDC-19204/6-To-IBM PC/XT/AT Theory of Operation
1. The port address where the SDC-19204/6 is located is hard
wired with jumpers into the 74LS688 address decoder. This
address is HEX 300 through 303 and is reserved for prototype
cards.
2. Address line A1 selects the upper or lower 8 bits of the
SDC-19204/6 to be placed on the Bus. When A1 is high, bits 1-
8 are selected.
3. Address line A0 sets and resets the SDC-19204/6 INHIBIT
(INH) line. When A0 is low, the INHIBIT command is invoked.
4. To read the output of the SDC-19204/6 perform the
following:
a. Send address HEX 302 to INHIBIT the SDC-19204/6
(hold data stable) and place bits 1-8 on the Bus. Read and
store data on D0 to D7.
b. Send address 300 HEX to keep the SDC-19204/6 in the
INHIBIT mode and place bits 9-14 on the Bus. Read and
store data on D0 to D7.
c. Read address 301 HEX or 303 HEX to release the
SDC-19204/6 from the INHIBIT mode and prepare for the
next measurement. No valid data will be on the bus during
this command.
5. Since the output data is not valid until 0.5
s after the INHIBIT
command is invoked, the l/O READY line is held low for this peri-
od of time. When l/O READY returns to the high level, the data
on the bus reads on the next negative clock edge.
500 nsec MIN PULSE
LATCH READ DATA
VALID ADDRESS
CLK
ALE
ADDR
I/O
READY
I/O R
OUT
IN
OUT
FIGURE 20. PC APPLICATION - I/O READ
CYCLE TIMING
IBM PC/XT/AT is a registered trademark of International Business Machines
Corporation.
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