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參數(shù)資料
| 型號： | SDC-19206-302 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP40 |
| 封裝： | 1.140 X 2.020 INCH, 0.230 INCH HEIGHT, TDIP-40 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 124K |
| 代理商： | SDC-19206-302 |
5
The digital output data changes approximately 50 ns after the
leading edge of the CB pulse because of an internal delay
(shown in FIGURE 1). Data is valid 0.2 s after the leading edge
of CB (see FIGURE 4). The angle is determined by the sum of
the bits at logic 1.
INHIBIT (INH, PIN 9)
When an Inhibit (INH) input is applied to the SDC-19204/6 the
Output Transparent Latch is locked, causing the output data bits
to remain stable while data is being transferred (see FIGURE 5).
The output data bits are stable 0.3
s after INH is driven to logic
0. A logic 0 at the T input of the Inhibit Transparent Latch latches
the data; a logic 1 applied to T allows the bits to change. This
latch also prevents the transmission of invalid data when there is
an overlap between CB and INH. While the counter is not being
updated, CB is at logic 0 and the INH latch is transparent; when
CB goes to logic 1, the INH latch is locked. If CB occurs after INH
has been applied, the latch will remain locked and its data will
not change until CB returns to logic 0; if INH is applied during
CB, the latch will not lock until the CB pulse is over. The purpose
of the 50 ns delay is to prevent a race condition between CB and
INH where the up-down counter begins to change as an INH is
applied.
An INH input, regardless of its duration, does not affect the con-
verter update. A simple method of interfacing to a computer
asynchronous to CB is:
(1) Apply INH.
(2) Wait 0.3
s, min.
(3) Transfer the data.
(4) Release INH.
As long as the converter maximum tracking rate is not exceed-
ed, there will be no velocity lag in the converter output although
momentary acceleration errors remain. If a step input occurs, as
when the power is initially applied, the response will be critically
damped. FIGURE 6 shows the response to a step input. After ini-
tial slewing at the maximum tracking rate of the converter, there
is one overshoot (which is inherent in a Type II servo). The over-
shoot settling to a final value is a function of the small signal set-
tling time.
DATA TRANSFERS
Digital output data from the SDC-19204/6 can be transferred to
8-bit and 16-bit bus systems. For 8-bit systems, the MSB and
LSB bytes are transferred sequentially (see FIGURES 7A and
7B). For 16-bit systems, all bits are transferred at the same time
(see FIGURES 8A and 8B).
;
DEPENDS UPON d
φ/dt
0.4-0.7
s
CB
0.2
s MAX
DATA
VALID
6.1
s MIN
;;
DATA
VALID
0.3
s MAX
ASYNCHROUS TO CB
INH
OVERSHOOT
SMALL SIGNAL
SETTLING TIME
MAX SLOPE EQUALS
TRACKING RATE (SLEW RATE)
θ2
θ1
FIGURE 4. CB TIMING
FIGURE 5. INHIBIT TIMING
FIGURE 6. RESPONSE TO A STEP INPUT
TABLE 2 DIGITAL ANGLE OUTPUTS
BIT
DEG/BIT
MIN/BIT
1 (MSB ALL MODES)
2
3
4
5
6
7
8
9
10 (LSB 10-BIT MODE)
11
12 (LSB 12-BIT MODE)
13
14 (LSB 14-BIT MODE)
15
16 (LSB 16-BIT MODE)
180
90
45
22.5
11.25
5.625
2.813
1.405
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
10800
5400
2700
1350
675
387.5
168.5
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
Note: EM enables the 8 MSBs and EL enables the LSBs.
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