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參數(shù)資料
| 型號(hào)： | SDC-19206-302 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP40 |
| 封裝： | 1.140 X 2.020 INCH, 0.230 INCH HEIGHT, TDIP-40 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 124K |
| 代理商： | SDC-19206-302 |
7
PROGRAMMABLE RESOLUTION
Resolution is controlled by two logic inputs, A and B (see TABLE
3). The resolution can be changed during converter operation so
the appropriate resolution and velocity dynamics can be
changed as needed. To insure that a race condition does not
exist between counting and changing the resolution, inputs A
and B are transferred through the latch internally on the trailing
edge of CB (see FIGURE 9).
FASTER SETTLING TIME USING BIT TO REDUCE
RESOLUTION
Since the SDC-19204/6 has higher precision in the higher reso-
lution mode and faster settling in the lower resolution modes, the
BIT output can be used to program the SDC-19204/6 for lower
resolution, allowing the converter to settle faster for step inputs.
High precision and fast settling can therefore be obtained simul-
taneously and automatically in one unit.
When the resolution is changed, the VEL scaling is also
changed. Since the VEL output is from an integrator with a
capacitor feedback, the VEL voltage cannot change instanta-
neously. Therefore, when changing resolution while moving there
will be a transient with a magnitude proportional to the velocity
and a duration determined by the converter bandwidth.
MAJOR CARRY (MC, PIN 32)
Major Carry is used with Direction Output (U) for multiturn appli-
cations. This signal is similar to a 4-bit up-down counter CO
(Carry Out), that is, it is normally high and goes low for all 1’s
when counting up or all 0’s when counting down. See FIGURE
10 for a typical interconnection.
DIRECTION OUTPUT (U, PIN 31)
Direction Output (U) timing is shown in FIGURE 11. It is at logic
1 to count up and logic 0 to count down. The logic level at (U) is
valid at least 0.5
s before and at least 20 ns after the leading
edge of CB.
SYSTEM SELF-TEST
The SDC-19204/6 provides two useful logic outputs for systems
self test: BIT and LOS.
BUILT-IN-TEST (BIT, PIN 29)
The Built-ln-Test (BIT) output monitors the level of error (D) from
the demodulator. D represents the difference in the input and
output angles and ideally should be zero. If it exceeds approxi-
mately 65 LSBs (of the selected resolution), the logic level at BIT
will change from a logic 1 to logic 0. This condition will occur dur-
ing a large step and reset after the converter settles out. BIT will
also change to logic 0 for an over-velocity condition because the
;
;;;;
DIRECTION (U)
0.5
s MIN
MAJOR CARRY
MC
;
DON'T CARE
UP
COUNT
DOWN
COUNT
20 ns MIN
0.5
s MIN
0.5
s MIN
0.5
s MIN
CB
0.5
s MIN
;;;
;;
A,B
VALID
0
s MIN
CB
0.1
s MIN
UP/DOWN
COUNTER
C0
C1
MC
U
CB
UT
SDC-19204/6
4 BITS
TURNS COUNTING
FIGURE 10. TURNS COUNTING CONNECTION
DIAGRAM
Notes:
(1) For the 4-bit up/down counter, use 74LS169B (TTL) or 4516 (CMOS).
(2) U = up/down line, logic 1 counts up.
(3) T = toggle line, counts on positive edge.
FIGURE 11. DIRECTION OUTPUT (U) TIMING
FIGURE 9. RESOLUTION CONTROL TIMING
TABLE 3. RESOLUTION CONTROL
B
(PIN 8)
A
(PIN 7)
RESOLUTION
0
1
0
1
0
1
10 BIT
12 BIT
14 BIT
16 BIT
Note: All unused digital output data bits are at logic 0.
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