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參數(shù)資料
| 型號： | SG2526N |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | REGULATING PULSE WIDTH MODULATOR |
| 中文描述： | 0.2 A SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDIP16 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 182K |
| 代理商： | SG2526N |
4/90 Rev 1.1 2/94
Copyright
1994
L
IN
F
IN
ITY
Microelectronics Inc.
11861 Western Avenue
∞
∞
Garden Grove, CA 92841
(714) 898-8121
∞
FAX: (714) 893-2570
7
SG1526/SG2526/SG3526
APPLICATION INFORMATION
(continued)
The oscillator is programmed for frequency and deadtime with three components: R
, C
, and R
. Two waveforms are
generated: a sawtooth waveform at pin 10 for pulse width modulation, and a logic clock at pin 12. The following procedure
is recommended for choosing timing values:
1. With R
= 0
(pin 11 shorted to ground) select values for R
and C
from Figure 7 to give the desired oscillator period.
Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +V
C
terminal
is the same as the oscillator frequency.
2. If more dead time is required, select a larger value of R
D
using Figure 6 as a guide. At 40kHz dead time increases by
400nSec/ohm.
3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of R
T
slightly to bring the frequency back to the nominal design value.
The SG1526 can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency 10% slower
than the sync frequency. A periodic LOW logic pulse approximately 0.5μSec wide at the SYNC pin will then lock the oscillator
to the external frequency.
Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then sharing
its sawtooth and clock waveforms with the slave units. All C
terminals are connected to the C
pin of the master, and all SYNC
terminals are likewise connected to the SYNC pin of the master. Slave R
terminals should not be left open nor should they
be tied to the +5V reference; at least 50K should be connected to each pin. Slave R
D
terminals may be either left open or
grounded.
OSCILLATOR
FIGURE 21 - OSCILLATOR CONNECTIONS AND WAVEFORMS
The error amplifier is a transconductance design, with an output impedance of 2 megohms and an effective output capacitance
of 100 pF. Since all voltage gain takes place at the output pin, the open-loop gain can be shaped with shunt reactance to ground.
For unity gain stability the amplifier requires an additional external 100 pF to ground, resulting in an open-loop pole at 400 Hz.
The input connections to the error amplifier are determined by the polarity of the switching supply output voltage. For positive
supplies, the common-mode voltage is +5.0 volts and the feedback connections in Figure 22A are used. With negative
supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the
+5.0 volt reference voltage, as shown in Figure 22B.
ERROR AMPLIFIER CONNECTIONS
FIGURE 22A
FIGURE 22B
ERROR AMPLIFIER
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