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參數(shù)資料
| 型號(hào)： | SHC5320SH |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | High-Speed, Bipolar, Monolithic SAMPLE/HOLD AMPLIFIER |
| 中文描述： | 高速，雙極，單片采樣/保持放大器 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 87K |
| 代理商： | SHC5320SH |
6
SHC5320
Charge Offset
(pedestal) is the output voltage change that
results from charge transfer into the hold capacitor through
stray capacitance when the Hold mode command is given.
This charge appears as an offset voltage at the output, and in
some sample/hold amplifiers may be a function of the input
voltage.
Charge offset is specified for the SHC5320 using only the
internal holding capacitor. When an external capacitor is
added, charge offset is calculated as Charge Transfer (pC)
divided by total hold capacitance. Charge Transfer is also
specified for the SHC5320, and total hold capacitance is the
sum of the internal hold capacitor value (100pF) and the
external hold capacitor. Since charge transfer is not a func-
tion of analog input voltage for the SHC5320, this error may
be removed by means of the offset adjustment capability of
the amplifier.
Droop Rate
is the change in output voltage over time during
the Hold mode as a result of hold capacitor leakage, switch
leakage, and bias current of the output amplifier. Droop rate
varies with temperature and the quality of the external
holding capacitor, if used. Careful circuit layout is also
required to minimize droop.
Drift Current
is the net leakage current affecting the hold
capacitor during the Hold mode. With knowledge of the drift
current, droop can be calculated as:
Droop (V/s) = I
D
(pA)/C
H
(pF)
Hold Mode Feedthrough
is the fraction of the input signal
which appears at the output while in the Hold mode. It is
primarily a function of switch capacitance, but may also be
increased by poor layout practices.
Hold Mode Settling Time
is the time required for the sample-
to-hold transient to settle within a specified error band.
OPERATING INSTRUCTIONS
(Developed Around 14-Pin Package)
OFFSET ADJUSTMENT
The offset should be adjusted with the input grounded.
During the adjustment, the sample/hold should be switching
continuously between the Sample and the Hold modes. The
offset should then be adjusted to zero output for the periods
when the amplifier is in the Hold mode. In this way, the
effects of both amplifier offset and charge offset will be
accounted for.
SAMPLE/HOLD CONTROL
A TTL logic “0” applied to pin 14 switches the SHC5320
into the Sample (track) mode. In this mode, the device acts
as an amplifier which exhibits normal operational amplifier
behavior, with the relationship of output to input signal
depending upon the circuit configuration selected (see the
Installation section below). Application of a logic “1” to pin
14 switches the SHC5320 into the Hold mode, with the
output voltage held constant at the value present when the
hold command is given. Pin 14 presents less than one
LSTTL load to the driving circuit throughout the full oper-
ating temperature range.
Teflon
Du Pont Corporation
ADDITION OF AN EXTERNAL CAPACITOR
The SHC5320 contains an internal 100pF MOS holding
capacitor, sufficient for most high-speed applications. If
improved droop performance is desired (with increased
acquisition time), additional capacitance may be added be-
tween pins 7 and 11. If an external holding capacitor C
is
used, then a noise-bandwidth capacitor with a value 0.1C
H
should be connected from pin 8 to ground. The exact value
and type of this bandwidth capacitor are not critical.
Capacitors with high insulation resistance and low dielectric
absorption,
such as Teflon
or polystyrene units
, should be
used as storage elements (polystyrene should not be used
above +85
°
C). Care should be taken in the printed circuit
layout to minimize leakage currents from the capacitor to
minimize droop errors.
The value of the external capacitor determines the droop,
charge offset, and acquisition time of the sample/hold. Both
droop and charge offset will vary linearly with total hold
capacitance from the values given in the specification table
for the internal 100pF capacitor. The behavior of acquisition
time versus total hold capacitance is shown in the Typical
Performance Curves.
OUTPUT PROTECTION
In order to optimize high-frequency performance of this
device, output protection is not included. This high fre-
quency performance is mandatory for a good sample/hold,
which must absorb high-frequency changes in load current
when driving a successive-approximation A/D converter.
Due to the lack of output protection, the output circuit will
not tolerate an indefinite short to common, but a momentary
short is permissible. The output should never be shorted to
a supply.
INSTALLATION
(Developed Around 14-Pin Package)
LAYOUT PRECAUTIONS
Since the holding capacitor is connected to virtual ground at
one end (pin 11) and to a low-impedance voltage source at
the other (pin 7), the SHC5320 does not require the use of
guard rings and other careful layout techniques which are
required by many sample/hold circuits. However, normal
good layout practice should be observed, minimizing the
possibility of leakage paths across the holding capacitor. As
in all digital-analog circuits, analog signal lines on the
circuit board should cross digital signal paths at right angles
whenever possible.
GROUNDING AND BYPASSING
Pin 6 (Reference Common) should be connected to the
system analog signal common as close to the unit as pos-
sible. Likewise, pin 13 (Supply Common) should be con-
nected to the system supply common. If the system design
prevents running these two common lines separately, they
should be connected together close to the unit, preferably to
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