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參數(shù)資料
| 型號(hào)： | SHC5320SH |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | High-Speed, Bipolar, Monolithic SAMPLE/HOLD AMPLIFIER |
| 中文描述： | 高速，雙極，單片采樣/保持放大器 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大小： | 87K |
| 代理商： | SHC5320SH |
9
SHC5320
FIGURE 10. PAM Output.
Hold
Sample
Mode
Control
Analog Input
PAM Output
DATA DISTRIBUTION
The SHC5320 may be used to hold the output of a digital-
to-analog converter and distribute several different analog
voltages to different loads (see Figure 11).
HIGH-SPEED DATA ACQUISITION
The minimum sample time for one channel in a data acqui-
sition system is usually considered to be the acquisition time
of the sample/hold plus the conversion time of the A/D
converter. If two or more sample/holds are used with a
multiplexer (such as the Burr-Brown MPC800 or MPC801)
as shown in Figure 12, the acquisition time of the sample/
hold can be virtually eliminated. While the first channel is in
hold and switched into the A/ D converter, the multiplexer
may be addressed to the next channel. The second sample/
hold will have acquired this signal by the time the conver-
sion is complete. Then, the sample/holds reverse roles and
another channel is addressed. In low level systems an instru-
mentation amplifier (such as the Burr-Brown INA101) and
a differential multiplexer (such as the Burr-Brown MPC509A
or MPC507A) may be required in front of the sample/hold.
The settling and acquisition times of the multiplexer, instru-
mentation amplifier, and sample/hold can be eliminated
from the total conversion time as before by operating in this
overlapped mode with the sample/holds.
Additional
SHC5320
Units
D/A
Converter
Parallel
Inputs
Digital
Inputs
Mode
Control
Logic
SHC5320
1
2
14
6
Analog
Outputs
Channel 1
SHC5320
1
2
14
6
Channel 2
SHC5320
1
2
14
6
Channel N
Signal
Common
7
7
7
FIGURE 11. Typical Data Distribution Configuration.
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