
Si2400
Rev. 1.3
47
SDF
0xDF
DGSR
This is a bit mapped register.1
0x00
SE0
0xE0
CF1
This is a bit mapped register.1
0x22
SE1
0xE1
CLK1
This is a bit mapped register.1
0x07
SE2
0xE2
GPIO
This is a bit mapped register.1
0x00
SE3
0xE3
GPD
This is a bit mapped register.1
0x00
SE4
0xE4
CF5
This is a bit mapped register.1
0x00
SE5
0xE5
DADL
(SE8 = 0x00) Write only definition. DSP register address lower
bits [7:0].1
0x00
SE5
0xE5
DDL
(SE8 = 0x01) Write only definition. DSP data word lower bits
[7:0].1
0x00
SE5
0xE5
DSP1
(SE8 = 0x02) Read only definition. This is a bit mapped register.1
0x00
SE5
0xE5
DSP2
(SE8 = 0x02) Write only definition. This is a bit mapped register.1
0x00
SE6
0xE6
DADH
(SE8 = 0x00) Write only definition. DSP register address upper
bits [15:8]
0x00
SE6
0xE6
DDH
(SE8 = 0x01) Write only definition. DSP data word upper bits
[13:8]
0x00
SE6
0xE6
DSP3
(SE8 = 0x02) Write only definition. This is a bit mapped register.1
0x00
SE8
0xE8
DSPR4
Set the mode to define E5 and E6 for low level DSP control.
0x00
SEB
0xEB
TPD
This is a bit mapped register.1
0x00
SF0
0xF0
DAA0
This is a bit mapped register.1
0x00
SF1
0xF1
DAA1
This is a bit mapped register.1
0x1C
SF2
0xF2
DAA2
This is a bit mapped register.1
0x00
SF4
0xF4
DAA4
This is a bit mapped register.1
0x0F
SF5
0xF5
DAA5
This is a bit mapped register.1
0x08
SF6
0xF6
DAA6
This is a bit mapped register.1
0x00
SF7
0xF7
DAA7
This is a bit mapped register.1
0x10
SF8
0xF8
DAA8
This is a bit mapped register.1
—
SF9
0xF9
DAA9
This is a bit mapped register.1
0x20
Table 27. S-Register Summary (Continued)
“S”
Register
Address
(hex)
Name
Function
Reset
Notes:
1. These registers are explained in detail in the following section.
2. The ring detector will only detect ringing if the ring burst on/off times meet the settings in MNRP, MXRP, MNRU, ROT,
and REP.