(VD = 3.0 to 3.6 V, T
參數(shù)資料
型號(hào): SI2439-A-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 69/70頁
文件大?。?/td> 0K
描述: IC ISOMODEM 33.6KBPS 38-QFN
標(biāo)準(zhǔn)包裝: 364
系列: *
Si2494/39
8
Rev. 1.0
Table 5. Switching Characteristics1
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for F-grade, TA = –40 to 85 °C for G-grade)
Parameter
Symbol
Min
Typ
Max
Unit
UART Timing Parameters
CLKOUT Output Clock Frequency
2.048
49.152
MHz
Baud Rate Accuracy
tBD
–1
1
%
Reset Timing Parameters
RESET
to RESET
tRS
5.02
——
ms
RESET
to 1st AT Command
tAT
300
ms
Parallel Timing Parameters
Address Setup
tAS
15
ns
Address Hold
tAH
0—
ns
WR Low Pulse Width
tWL
50
ns
Write Data Setup Time
tWDSU
20
ns
Write Cycle Time
tWC
120
ns
Chip Select Setup
tCSS
10
ns
Chip Select Hold
tCSH
0—
ns
RD Low Pulse Width
tRL
50
ns
RD Low to Data Driven Time
tRLDD
20
ns
Data Hold
tDH
10
ns
RD High to Hi-Z Time
tDZ
30
ns
Read Cycle Time
tRC
120
ns
Write to Read Cycle Time
tWRC
120
ns
Serial Peripheral Interface (SPI) Timing Parameters
SS Falling to First SCLK Edge
tSE
41
ns
Last SCLK Edge to SS Rising
tSD
41
ns
SS Rising to MISO High-Z
tSDZ
93
ns
SCLK High Time
tCKH
102
ns
SCLK Low Time
tCKL
102
ns
MOSI Valid to SCLK Sample Edge
tSIS
41
ns
SCLK Sample Edge to MOSI Change
tSIH
41
ns
SCLK Shift Edge to MISO Change
tSOH
93
ns
Notes:
1.
All timing is referenced to the 50% level of the waveform. Input test levels are VIH =VD – 0.4 V, VIL =0.4 V.
2.
With 32.768 kHz clocking, allow 500 to the reset low-to-high minimum pulse on power-up and wake-from-power-down
conditions.
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