參數(shù)資料
型號(hào)： SI3015-BS
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 18/64頁(yè)
文件大小： 0K
描述： IC ISOMODEM LINE-SIDE DAA 16SOIC
標(biāo)準(zhǔn)包裝： 48
系列： ISOmodem®
數(shù)據(jù)格式： V.90
波特率： 2.4k
電源電壓： 3.3V，5V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
Si3038
Rev. 2.01
25
zero. The length of this count (in seconds) is 65536
divided by the sample rate. The GPIO1(GPIO11) bit will
also be reset to zero by an off-hook event.
When RFWE is 1, the GPIO1(GPIO11) bit will toggle
active low when the ring signal is positive or negative.
This makes the ring signal appear to be twice the
frequency of the ringing waveform.
The RDTP and RDTN behavior is based on the RNG1-
RNG2 voltage. Whenever the signal RNG1-RNG2 is
above the positive ring threshold the RDTP bit is set.
Whenever the signal RNG1-RNG2 is below the
negative ring threshold the RDTN bit is set. When the
signal RNG1-RNG2 is between these thresholds,
neither bit is set.
If the ISOcap is active and the device is not off-hook or
not in on-hook line monitor mode, the ring data will be
presented on SDATA_IN. The waveform on SDATA_IN
depends on the state of the RFWE bit.
When RFWE is 0, SDATA_IN will be –32768 (8000h)
while the RNG1-RNG2 voltage is between the
thresholds. When a ring is detected, SDATA_IN will
transition rather quickly to +32767 while the ring signal
is positive, then go back to –32768 while the ring is near
zero and negative. Thus a near square wave is
presented on SDATA_IN that swings from –32768 to
+32767 in cadence with the ring signal.
When RFWE is 1, SDATA_IN will sit at approximately
+1228 while the RNG1-RNG2 voltage is between the
thresholds. When the ring goes positive, SDATA_IN will
transition to +32767. When the ring signal goes near
zero, SDATA_IN will remain near 1228. Then as the ring
goes negative, the SDATA_IN will transition to –32768.
This will repeat in cadence with the ring signal.
The best way to observe the ring signal on SDATA_IN is
simply to observe the MSB of the data. The MSB will
toggle in cadence with the ring signal independent of
the ring detector mode. This is adequate information for
determining the ring frequency. The MSB of SDATA_IN
will toggle at the same frequency as the ring signal.
Ringer Impedance
The ring detector in many DAAs is ac coupled to the line
with a large, 1 uF, 250 V decoupling capacitor. The ring
detector on the Si3038 is also capacitively coupled to
the line, but it is designed to use smaller, less expensive
capacitors (C7, C8). Inherently, this network produces a
high ringer impedance to the line of approximately 800
to 900 k
. This value meets the majority of country PTT
specifications, including FCC and CTR21.
Several countries including Poland, South Africa and
Slovenia, require a maximum ringer impedance that can
be met with an internally synthesized impedance by
setting the RZ bit in register 5Ch.
Wake-Up on Ring
Ring is an example of an event that might need to wake-
up a PC that has suspended into a low-power state.
Power management, or wake, event support for a modem
is a key feature of the current PC industry standards.
The Si3038 provides wake-up on ring through the AC-
link as defined by the AC’97 ver 2.1 specification. In an
implementation designed for wake-on ring, where the
Si3038 and AC-link are both completely powered by
Vaux, a ring detected at the RNG1 and RNG2 pins of
the Si3038 causes the assertion of the power
management signal to the system. The power
management signal is the rising edge of the SDATA_IN
signal when the Si3038 is in low-power mode. The
power management event signal assertion causes the
system to resume so that the modem event (ring) can
be serviced. The first thing that the device driver must
do to reestablish communications with the Si3038 is to
command the AC’97 Digital Controller to execute a
warm reset to the AC-link. Figure 24 illustrates the
entire sequence.
The rising edge of SDATA_IN causes the AC’97 Digital
Controller to assert its power management signal to the
system’s ACPI controller. The Si3038 will keep
SDATA_IN high until it has sampled SYNC having gone
high, and then Low (warm reset). The power
management event is cleared out in the AC’97 Digital
Controller by system software, asynchronous to AC-link
activity. The AC’97 Digital Controller should always
monitor the Si3038’s ready bit before sending data to it.
The modem driver should read the GPIO Pin Status
register to determine if the wake event was due to the
ring signal before executing a register reset.
Before entering the low-power mode, the Si3038 must
be enabled to cause the wake signal when receiving a
ring. This is done by programming the GPIO Pin Sticky
(50h) and GPIO Wake Up Mask (52h) registers and
clearing previous sticky GPIO events. Before setting the
MLNK bit the driver should do the following:
1. Set the GS1 bit in register 50h (GS11 if using line #2)
2. Set the GW1 bit in register 52h (GW11 for line #2)
3. Clear a possible old sticky event by writing a 0 to the GI1
(GI11 for line #2) bit in read only register GPIO Pin Status
register (54h).
If the AC’97 Digital Controller allows the RESET signal
to go low during the low-power mode of the Si3038. The
wake event will be a cold reset (rising edge of RESET)
and the modem driver should re-program the GPIO Pin
Sticky register to set the GS1 (or GS11) bit. This will
allow the modem driver to read the sticky value of the
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SI3015-E-FSR 制造商:Silicon Laboratories Inc 功能描述:
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SI3015-F-FSR 制造商:Silicon Laboratories Inc 功能描述:Modem Chip Chipset 2.4Kbps 16-Pin SOIC T/R 制造商:Silicon Laboratories Inc 功能描述:MODEM CHIP CHIPSET ISOMODEM 2.4KBPS 16SOIC - Tape and Reel 制造商:Silicon Laboratories 功能描述:Modem Chip Chipset 2.4Kbps 16-Pin SOIC T/R
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