參數(shù)資料
型號: SI3216DCQX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 34/122頁
文件大?。?/td> 0K
描述: DAUGHTER CARD W/DISCRETE INTRFC
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3216
已供物品: 板,CD
Si3216
Rev. 1.0
19
Not
Recommended
fo
r N
ew
D
esi
gn
s
Figure 9. SPI Timing Diagram
Table 12. Switching Characteristics—PCM Highway Serial Interface
VD = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL =20 pF
Parameter
Symbol
Test
Conditions
Min 1
Typ 1
Max 1
Units
PCLK Frequency
1/tc
0.256
0.512
0.768
1.024
1.536
2.048
4.096
8.192
MHz
PCLK Duty Cycle Tolerance
tdty
40
50
60
%
PCLK Period Jitter Tolerance
tjitter
–120
120
ns
Rise Time, PCLK
tr
——
25
ns
Fall Time, PCLK
tf
——
25
ns
Delay Time, PCLK Rise to DTX Active
td1
——
20
ns
Delay Time, PCLK Rise to DTX
Transition
td2
——
20
ns
Delay Time, PCLK Rise to DTX Tri-state2
td3
——
20
ns
Setup Time, FSYNC to PCLK Fall
tsu1
25
ns
Hold Time, FSYNC to PCLK Fall
th1
20
ns
Setup Time, DRX to PCLK Fall
tsu2
25
ns
Hold Time, DRX to PCLK Fall
th2
20
ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4 V, VIL =0.4 V.
2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
SCLK
CS
SDI
t
h1
t
d3
SDO
t
d1
t
d2
t
su1
t
r
t
r
t
c
t
su2
t
h2
t
cs
t
thru
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