- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16210 > SI3216DCQX-EVB (Silicon Laboratories Inc)DAUGHTER CARD W/DISCRETE INTRFC PDF資料下載
參數(shù)資料
| 型號(hào)： | SI3216DCQX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 56/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/DISCRETE INTRFC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3216 |
| 已供物品： | 板，CD |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)當(dāng)前第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)
Si3216
Rev. 1.0
39
Not
Recommended
fo
r N
ew
D
esi
gn
s
2.3.4. Enhanced FSK Waveform Generation
Enhanced FSK generation capabilities can be enabled
by setting FSKEN = 1 (direct Register 108, bit 6) and
REN = 1 (direct Register 32, bit 6). In this mode, the
user can define mark (1) and space (0) attributes once
during initialization by defining indirect Registers 69–74.
The user need only indicate 0-to-1 and 1-to-0 transitions
in the information stream. By writing to FSKDAT (direct
Register 52), this mode applies a 24 kHz sample rate to
tone generator 1 to give additional resolution to timers
and frequency generation. “AN32: Si321x Frequency
Shift
Keying
(FSK)
Modulation”
gives
detailed
instructions on how to implement FSK in this mode.
Additionally, sample source code is available from
Silicon Laboratories upon request.
2.3.5. Tone Generator Interrupts
Both the active and inactive timers can generate their
own interrupt to signal “on/off” transitions to the
software. The timer interrupts for tone generator 1 can
be individually enabled by setting the O1AE and O1IE
bits (direct Register 21, bits 0 and 1, respectively).
Timer interrupts for tone generator 2 are O2AE and
O2IE (direct Register 21, bits 2 and 3, respectively). A
pending interrupt for each of the timers is determined by
reading the O1AP, O1IP, O2AP, and O2IP bits in the
Interrupt Status 1 register (direct Register 18, bits 0
through 3, respectively).
2.4. Ringing Generation
The ProSLIC provides fully-programmable internal
balanced ringing with or without a dc offset to ring a
wide variety of terminal devices. All parameters
associated with ringing are software-programmable:
ringing frequency, waveform, amplitude, dc offset, and
ringing cadence. Both sinusoidal and trapezoidal ringing
waveforms are supported, and the trapezoidal crest
factor is programmable. Ringing signals of up to 90 V
peak or more can be generated, enabling the ProSLIC
to drive a 5 REN (1380
+ 40 F) ringer load across
loop lengths of 2000 feet (160
) or more.
2.4.1. Ringing Architecture
The ringing generator architecture is nearly identical to
that of the tone generator. The sinusoid ringing
waveform is generated using an internal two-pole
resonance
oscillator
circuit
with
programmable
frequency and amplitude. However, since ringing
frequencies are very low compared to the audio band
signaling
frequencies,
the
ringing
waveform
is
generated at a 1 kHz rate instead of 8 kHz.
The ringing generator has two timers that function the
same as for the tone generator timers. They allow on/off
cadence settings up to 8 seconds on/ 8 seconds off. In
addition to controlling ringing cadence, these timers
control the transition into and out of the Ringing state.
Table 29 summarizes the list of registers used for
ringing generation.
Note: Tone generator 2 should not be enabled concurrently
with the ringing generator due to resource sharing
within the hardware.
When
the
Ringing
state
is
invoked
by
writing
LF[2:0] = 100 (direct Register 64), the ProSLIC goes
into the Ringing state and starts the first ring. At the
expiration of RAT, the ProSLIC turns off the ringing
waveform and goes to the on-hook transmission state.
Upon expiration of RIT, ringing again initiates. This
process continues as long as the two timers are
enabled and the Linefeed Control register is set to the
Ringing state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M3DRK-2406J | IDC CABLE - MKR24K/MC26G/MPR24K |
| ECM28DCBI | CONN EDGECARD 56POS R/A .156 SLD |
| GCM22DRMN | CONN EDGECARD 44POS .156 WW |
| CW252016-18NG | INDUCTOR 18NH 1008 SMD |
| SI3230MPPQX-EVB | BOARD EVAL W/DISCRETE INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI3216-FT | 功能描述:IC SLIC/CODEC 1CH 38TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:ProSLIC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| SI3216-GT | 功能描述:IC SLIC/CODEC 1CH 38TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:ProSLIC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| SI3216-KT | 功能描述:IC SLIC/CODEC 1CH 38TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:ProSLIC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| SI3216-KTR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3216M-B-FM | 功能描述:IC SLIC/CODEC 1CH 38QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:ProSLIC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。