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參數(shù)資料
| 型號(hào)： | SI3220DC0-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 83/112頁 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3220 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
72
Rev. 1.3
Not
Recommended
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The receive path transfer function requirement, shown
in Figure 8 on page 23, is very similar to the transmit
path transfer function. The PCM data rate is 8 kHz; so,
no frequencies greater than 4 kHz are digitally-encoded
in the data stream. At frequencies greater than 4 kHz,
the plot in Figure 8 is interpreted as the maximum
allowable magnitude of spurious signals that are
generated when a PCM data stream representing a sine
wave signal in the range of 300 Hz to 3.4 kHz at a level
of 0 dBm0 is applied at the digital input.
The group delay distortion in either path is limited to no
more than the levels indicated in Figure 9 on page 24.
The reference in Figure 9 is the smallest group delay for
a sine wave in the range of 500 Hz to 2500 Hz at
0 dBm0.
The block diagram for the voice-band signal processing
paths is shown in Figure 11 on page 25. Both the
receive and the transmit paths employ the optimal
combination of analog and digital signal processing for
maximum performance while maintaining sufficient
flexibility for users to optimize their particular application
of the device. The two-wire (TIP/RING) voice-band
interface to the device is implemented with a small
number of external components. The receive path
interface consists of a unity-gain current buffer, IBUF,
while the transmit path interface is an ac coupling
capacitor.
Signal
paths,
although
implemented
differentially, are shown as single-ended for simplicity.
3.26. System Clock Generation
The Dual ProSLIC devices generate the internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 786 kHz,
1.024 MHz,
1.536 MHz,
1.544 MHz,
2.048 MHz,
4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to
the FSYNC rate is determined by a counter clocked by
PCLK. The three-bit ratio information is transferred into
an internal register, PLL_MULT, after a device reset.
The PLL_MULT controls the internal PLL, which
multiplies PCLK to generate the rate required to run the
internal filters and other circuitry.
The PLL clock synthesizer settles quickly after power-
up or update of the PLL-MULT register. The PLL lock
process begins immediately after the RESET pin is
pulled high and takes approximately 5 ms to achieve
lock after RESET is released with stable PCLK and
FSYNC. However, the settling time depends on the
PCLK frequency and can be predicted based on the
following equation:
Note: Therefore, the RESET pin must be held low during
powerup and should only be released when both
PCLK and FSYNC signals are known to be stable.
Figure 40. PLL Frequency Synthesizer
T
settle
64
f
PCLK
---------------
=
PFD
DIV M
PLL_MULT
VCO
÷2
RESET
28.672 MHz
PCLK
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