參數(shù)資料
型號(hào): SI3232-G-GQ
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 77/128頁(yè)
文件大?。?/td> 0K
描述: IC SLIC PROG DUAL-CH 64TQFP
標(biāo)準(zhǔn)包裝: 160
功能: 用戶線路接口概念(SLIC)
接口: ISDN
電路數(shù): 2
電源電壓: 3.13 V ~ 3.47 V
電流 - 電源: 28mA
功率(瓦特): 280mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)當(dāng)前第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
Si3232
52
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
4.17. Si3232 RAM and Register Space
The
Si3232
is
a
highly-programmable
telephone
linecard solution that uses internal registers and RAM to
program operational parameters and modes. The
Register Summary and RAM Summary are compressed
listings for single-entry quick reference. The Register
Descriptions and RAM Descriptions give detailed
information of each register or RAM location’s bits.
All RAM locations are cleared upon a hardware reset.
All RAM locations that are listed as “INIT” must be
initialized to a meaningful value for proper functionality.
Bit 4 of the MSTRSTAT register indicates the clearing
process is finished. This bit should be checked before
initializing the RAM space.
Accessing register and RAM space is performed
through the SPI. Register space is accessed by using
the standard three-byte access as described in the next
section. Bit 5 of the control byte specifies register
access when set to a 1. All register space is comprised
of 8-bit data.
4.17.1. RAM Access by Pipeline
Ram space can be accessed by two different methods.
One method is a pipeline method that employs a 4-byte
access plus a RAM status check. The control byte for
the pipeline method has bit 6 cleared to 0 to indicate a
RAM access. The control byte is followed by the RAM
address byte, then the two data bytes.
Reading RAM in the pipeline method requires “priming”
the data. First, check for register RAMSTAT, bit 0, to
indicate the previous access is complete and RAM is
ready (0). Then, perform the 4-byte RAM access. The
first read will yield unusable data. The data read on the
subsequent read access is the data for the previous
address read. A final address read yields the last
previously-requested data. The RAM-ready information
(RAMSTAT) must be read before every RAM access.
To write a RAM location, check for register RAMSTAT,
bit 0, to indicate the previous access is complete and
RAM is ready (0). Then, write the RAM address and
data in the 4-byte method. A write to RAM location
requires “priming” the data with subsequent accesses.
4.17.2. RAM Access by Register
An alternative method to access RAM space utilizes
three registers in sequence and monitors RAMSTAT
register, bit 0. These three registers are RAMADDR,
RAMDATLO, and RAMDATHI.
To read a RAM location in the Si3232, check for register
RAMSTAT (bit 0) to indicate the previous access is
complete and RAM is ready (0). Then, write the RAM
address to RAMADDR. Wait until RAMSTAT (bit 0) is a
1; then, the 16 bits of data can be read from the
RAMDATLO and RAMDATHI registers.
To write a RAM location in the Si3232, check for register
RAMSTAT (bit 0) to indicate the previous access is
completed and RAM is ready (0); then, write the 16 bits
of RAM data to the RAMDATLO, RAMDATHI. Finally,
write the RAM address to the RAMADDR register.
4.17.3. Chip Select
For register or RAM space access, there are three ways
to use chip select: byte length, 16-bit length, and access
duration length. The byte length method releases chip
select after every 8 bits of communication with the
Si3232. The time between chip select assertions must
be at least 220 ns.
The 16-bit length chip select method is similar to the
byte
length
method
except
that
16-bits
are
communicated with the Si3232. This means that Si3232
communication consists of a control byte, address byte
for one 16-bit access, and two data bytes for a second
16-bit access.
In a single data byte communication (control byte,
address byte, data byte), the data byte should be
loaded into either the high byte or both bytes of the
second 16-bit access for a write. The 8-bit data exists in
the high and low byte of a 16-bit access for a read. The
time between chip select assertion must be at least
220 ns.
Access duration length allows chip select to be pulled
low for the length of a number of Si3232 accesses.
There are two very specific rules for this type of
communication. One rule is that the SCLK must be of a
frequency that is less than 1/2x220 ns (<2.25 MHz).
The second rule is that access must be done in a 16-bit
modulus. This 16-bit modulus follows the same rules as
described above for 16-bit length access where 8-bit
data is concerned.
4.17.4. Protected Register Bits
The Si3232 has protected register bits that are meant to
retain the integrity of the Si3232 circuit in the event of
unintentional software register access. To access the
user-protected bits, write the following sequence of data
bytes to register address 87 (0x57):
0x02
0x10
0x12
0x00
Following the modification of any protected bit, the
same sequence should be immediately written to place
these bits into their protected state.
Protected bits exist in registers SBIAS and THERM.
相關(guān)PDF資料
PDF描述
VI-BNL-IY-B1 CONVERTER MOD DC/DC 28V 50W
VI-2TY-IW-F3 CONVERTER MOD DC/DC 3.3V 66W
SI3225-G-FQ IC PROSLIC/CODEC DUAL 64TQFP
VI-2TX-IY-F1 CONVERTER MOD DC/DC 5.2V 50W
VI-2TW-IY-F1 CONVERTER MOD DC/DC 5.5V 50W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI3232-G-GQR 功能描述:電信線路管理 IC Dual-CH SLIC only Internal 65 Vrms RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3232-KQ 功能描述:電信線路管理 IC DUAL CH SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3232PPT0-EVB 功能描述:音頻 IC 開(kāi)發(fā)工具 Si3232 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
SI3232PPTX-EVB 功能描述:音頻 IC 開(kāi)發(fā)工具 Si3232 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
SI3232-X-FQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING