5. 8-Bit Control Register Summary1,2
參數(shù)資料
型號： SI3232PPTX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 87/128頁
文件大?。?/td> 0K
描述： BOARD EVAL W/DISCRETE INTERFACE
標準包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3232
已供物品： 板，CD
Si3232
Preliminary Rev. 0.96
61
Not
Recommended
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5. 8-Bit Control Register Summary1,2
Any register not listed here is reserved and must not be written. Shaded registers are read only. All registers are
assigned a default value during initialization and following a system reset. Only registers 0, 2, 3, and 14 are
available until a PLL lock is established or during a clock failure.
(Ordered alphabetically by mnemonic.)
Reg
Addr3
Mnemonic
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
Def.
Hex
Audio
21
AUDGAIN
Audio Gain Control
CMTXSEL
ATXMUTE
ATX
ARXMUTE
ARX[1:0]
Init
R/W
0x00
Calibration
11
CALR1
Calibration Register 1
CAL
CALOFFR
CALOFFT
CALOFFRN
CALOFFTN
CALDIFG
CALCMG
Init
R/W
0x3F
12
CALR2
Calibration Register 2
CALLKGR
CALLKGT
CALMADC
CALDACO
CALADCO
CALCMBAL
Init
R/W
0x3F
Diagnostic Tools
13
DIAG
Diagnostics Tool Enable
IQ2HR
IQ1HR
TSTRING
TXFILT
SDIAG
SDIAGIN[2:0]
Diag
R/W
Chip ID
0ID
Chip ID
PARTNUM[2:0]4
REV[3:0]4
Init
R
0x—
Loop Current Limit
10
ILIM
Loop Current Limit
ILIM[4:0]
Init
R/W
0x05
Interrupts
14
IRQ0
Interrupt Status 0
CLKIRQ4,6
IRQ3B4,6
IRQ2B4,6
IRQ1B4,6
IRQ3A4,6
IRQ2A4,6
IRQ1A4,6
Oper
R
0x00
15
IRQ1
Interrupt Status 1
PULSTAS
PULSTIS
RINGTAS
RINGTIS
Oper
R/W
0x00
16
IRQ2
Interrupt Status 2
RAMIRS
DTMFS
VOCTRKS
LONGS
LOOPS
RTRIPS
Oper
R/W
0x00
17
IRQ3
Interrupt Status 3
CMBALS
PQ6S
PQ5S
PQ4S
PQ3S
PQ2S
PQ1S
Oper
R/W
0x00
18
IRQEN1
Interrupt Enable 1
PULSTAE
PULSTIE
RINGTAE
RINGTIE
Init
R/W
0x00
19
IRQEN2
Interrupt Enable 2
RAMIRE
DTMFE
VOCTRKE
LONGE
LOOPE
RTRIPE
Init
R/W
0x00
20
IRQEN3
Interrupt Enable 3
CMBALE
PQ6E
PQ5E
PQ4E
PQ3E
PQ2E
PQ1E
Init
R/W
0x00
Loopback Enable
22
LBCON
Loopback Enable
DLM
Diag
R/W
0x00
Linefeed Control
9
LCRRTP
Loop Closure/Ring Trip/
Ground Key Detection
CMH4
SPEED4
VOCTST4
LONGHI4
RTP4
LCR4
Oper
R
0x40
6LINEFEED
Linefeed
LFS[2:0]4
LF[2:0]
Oper
R/W
0x00
SPI
2
MSTREN
Master Initialization
Enable
PLLFLT
FSFLT
PCFLT
Init
R/W
0x00
3
MSTRSTAT
Master Initialization
Status
PLLFAULT
FSFAULT
PCFAULT
SRCLR4
PLOCK4
FSDET4
FSVAL4
PCVAL4
Init
R/W
0x00
Pulse Metering
28
PMCON
Pulse Metering Control
ENSYNC4,7
TAEN17
TIEN17
PULSE17
Oper
R/W
0x00
30
PMTAHI
Pulse Metering Oscillator
Active Timer—
High Byte
PULSETA[15:8]7
Init
R/W
0x00
29
PMTALO
Pulse Metering Oscillator
Active Timer—
Low Byte
PULSETA[7:0]7
Init
R/W
0x00
Notes:
1.
Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the
PLL is not locked (MSTRSTAT[PLOCK]).
2.
Reserved bit values are indeterminate.
3.
Register address is in decimal.
4.
Read only.
5.
Protected bits.
6.
Per-channel bit(s).
7.
Si3220 only.
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