參數(shù)資料
型號(hào)： SI3452-B01-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 11/36頁(yè)
文件大?。?/td> 0K
描述： IC POE CONTROLLER MIDSPAN 40QFN
特色產(chǎn)品： Si3452 Quad High-Voltage Port Controller for PoE and PoE+PSEs
標(biāo)準(zhǔn)包裝： 50
控制器類型： 以太網(wǎng)供電控制器（POE）
接口： I²C
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 14mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 管件
配用： SMARTPSE24-KIT-ND - KIT EVAL REF 24PORT SPI/UART
SI3480MS8-KIT-ND - KIT EVAL 8PORT SI3480/52/SI3500
其它名稱： 336-1829-5
Si3452
Rev. 1.3
19
5.5. Command and Return Registers (Registers 0x12–0x1C)
The global command register enables manual port turn-on or turn-off, chip reset, port reset, and measurement of
port current and VEE. Register 0x12 is a Write only register. See Table 24 on page 24 for a list of all available
commands.
If the command results in a numerical return value, that value is stored in the measurement registers, which are
read-only. Each of the five possible measurements results in a 2 byte return value, and that value is stored in a
unique register. VEE is encoded in mV units; so, the full scale is 65.535 V. Iport is encoded in 100 A units; so, the
full scale is 6.5535 A.
The output data is updated by the proper command register write operation (see Table 23). This means that the
numerical value of the port current or VEE voltage in the measurement register will be the value at the time the
command was issued. If the port turns off due to an overload or disconnect, the port current register contents will
not be set to zero. If a command to read port current is issued and the port is off, the return value will be zero.
5.6. Device Status Register (0x1D)
The device event bits are listed in Table 18.
The Device status register is RO. The VEE, UVLO, and overtemp bits reflect the device status. They are set if VEE
or temperature is out of range and reset if the VEE or temperature is in range. Bit 6 of the Interrupt register is set if
there is a change in the overtemp status (bit 6 of 0x1D), and bit 5 of the Interrupt register is set if there is a change
in the VEE UVLO status (bit 5 of 0x1D). Reading register 0x1D clears these bits of the Interrupt register but does
not clear the device status register.
In addition, bit B0 indicates whether or not detection back-off is used. For PSEs that are wired as Alternative B
(power on the spare pair–typically used for midspans), the time between detection pulses is increased to slightly
over two seconds to avoid interference with Alternative A (power on the data pair–typically used for endpoints). Bit
B0 can be toggled using the 0x10 command code.
Table 18. Device Status Bits
Bit
Description
B6—OverTemp
The Si3452 has per-port thermal shutdown sensors as well a global thermal shutdown
at a slightly higher temperature. The global thermal shutdown bit of the device event
register is set if this occurs.
B5—VEE UVLO
VEE UVLO. The part is put in its reset state if VEE is not in a valid range.
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