參數(shù)資料
型號(hào): SI3452-B01-GM
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 26/36頁(yè)
文件大小: 0K
描述: IC POE CONTROLLER MIDSPAN 40QFN
特色產(chǎn)品: Si3452 Quad High-Voltage Port Controller for PoE and PoE+PSEs
標(biāo)準(zhǔn)包裝: 50
控制器類型: 以太網(wǎng)供電控制器(POE)
接口: I²C
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 14mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 管件
配用: SMARTPSE24-KIT-ND - KIT EVAL REF 24PORT SPI/UART
SI3480MS8-KIT-ND - KIT EVAL 8PORT SI3480/52/SI3500
其它名稱: 336-1829-5
Si3452
32
Rev. 1.3
11. Recommended PCB Footprint
Figure 8. PCB Land Pattern
Table 27. PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
5.80
5.90
X2
4.10
4.20
C2
5.80
5.90
Y1
0.75
0.85
e
0.50 BSC
Y2
4.10
4.20
X1
0.15
0.25
Notes:
General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4.
All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5.
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60
m minimum, all the way around the pad.
Stencil Design
6.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
7.
The stencil thickness should be 0.125 mm (5 mils).
8.
The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9.
A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground pad.
Card Assembly
10.
A No-Clean, Type-3 solder paste is recommended.
11.
Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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