參數(shù)資料
型號: SI5013-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 11/26頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR SI5013
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘和數(shù)據(jù)恢復(fù)(CDR)
已用 IC / 零件: SI5013
已供物品:
其它名稱: 336-1123
Si5013
Rev. 1.6
19
5. Pin Descriptions: Si5013
Figure 15. Si5013 Pin Configuration
Table 8. Si5013 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1
RATESEL
I
LVTTL
Data Rate Select.
This pin configures the onboard PLL for clock and
data recovery at one of two user selectable data
rates. See Table 7 for configuration settings.
Notes:
1. This input has a weak internal pullup.
2. After any change in RATESEL, the device must be
reset.
3LOS_LVL
I
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 13 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
4
SLICE_LVL
I
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
GND
Pad
1
2
3
4
5
GND
LOS_LVL
REFCLK+
RATESEL
SLICE_LVL
6
7
LOL
REFCLK–
21
20
19
18
17
REXT
RESET/CAL
DOUT+
VDD
16
15
TDI
DOUT–
8
9
10 11 12
LO
S
DS
QLC
H
DI
N+
LTR
VD
D
13 14
VD
D
DI
N–
28 27 26 25 24
B
E
R
_A
LM
BER
_
L
VL
CL
KD
SBL
NC
VDD
23 22
CL
KO
UT
CL
KO
UT
+
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