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參數(shù)資料
| 型號： | SI5110-G-BC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SERIAL/DESERIAL 99BGA |
| 標準包裝： | 176 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-BCBGA |
| 供應(yīng)商設(shè)備封裝： | 99-CBGA（11x11） |
| 包裝： | 托盤 |
| 其它名稱： | 336-1181 |
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Si5110
Rev. 1.5
29
D8
RXMSBSEL
I
LVTTL
Receive Data Bus Bit Order Select.
This input determines the order of the received data
bits on the RXDOUT[3:0] output bus.
For RXMSBSEL = 0, the first data bit received is out-
put on RXDOUT0 and following data bits are output
on RDOUT1 through RXDOUT3.
For RXMSBSEL = 1, the first data bit is output on
RXDOUT3 and following data bits are output on
RXDOUT2 through RXDOUT0.
Note: This input has an internal pulldown.
A4
RXREXT
Receiver External Bias Resistor.
This resistor is used by the receiver circuitry to estab-
lish bias currents within the device. This pin must be
connected to GND through a 3.09 k
1resistor.
A5
RXSQLCH
I
LVTTL
Receiver Data Squelch.
When this input is low, the data on RXDOUT[3:0] is
forced to a zero state. Set RXSQLCH high for normal
operation.
The RXSQLCH input is ignored when operating in
Diagnostic Loopback mode (DLBK = 0).
Note: This input has an internal pullup.
A3
SLICELVL
I
Slicing Level Adjustment.
Applying an analog voltage to this pin allows adjust-
ment of the slicing level applied to the input data eye.
Tying this input to VREF sets the slicing offset to 0.
C6
SLICEMODE
I
LVTTL
Slice Level Adjustment Mode.
The SLICEMODE input is used to select the mode of
operation for slicing level adjustment. When SLICE-
MODE = 0, Absolute Slice mode is selected. When
SLICEMODE = 1, Proportional Slice mode is selected.
Note: This input has an internal pulldown.
K8
K7
TXCLK4IN+,
TXCLK4IN–
ILVDS
Differential Transmit Data Clock Input.
The rising edge of this input clocks data present on
TXDIN into the device. TXCLK 4IN is also used as the
Si5100 reference clock when the REFSEL input is set
low.
K6
K5
TXCLK4OUT+,
TXCLK4OUT–
OLVDS
Divided Down Transmit Clock Output.
This clock output is generated by dividing down the
high-speed output clock, TXCLKOUT, by a factor of 4.
It is intended for use in counter clocking schemes that
transfer data between the system framer and the
Si5110. (See REFSEL and REFRATE descriptions.)
Pin
Number(s)
Name
I/O
Signal Level
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5110-H-BL | 功能描述:電信線路管理 IC OC-48 STM-16 SONET SDH Trnscvr 1:16 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| Si5110-H-GL | 功能描述:電信線路管理 IC OC-48 STM-16 SONET SDH Trnscvr 1:16 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI5110-H-XL4 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI5110-H-ZL3 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI511BBA200M000BAGR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI511BBA200M000BAGR OSC (200MHZ) |
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