Si5330
6
Rev. 1.1
LVPECL Output Voltage
VOC
common mode
—
VDDO –
1.45 V
—V
VSEPP
peak-to-peak single-
ended swing
0.55
0.8
0.96
VPP
LVDS Output Voltage
(2.5/3.3 V)
VOC
common mode
1.125
1.2
1.275
V
VSEPP
peak-to-peak single-
ended swing
0.25
0.35
0.45
VPP
LVDS Output Voltage
(1.8 V)
VOC
common mode
0.8
0.875
0.95
V
VSEPP
peak-to-peak single-
ended swing
0.25
0.35
0.45
VPP
HCSL Output Voltage
VOC
common mode
0.35
0.375
0.400
V
VSEPP
peak-to-peak single-
ended swing
0.575
0.725
0.85
VPP
Rise/Fall Time
tR/tF
20%–80%
—
450
ps
Duty Cycle*
DC
CKn < 350 MHz
45
—
55
%
350 MHz < CLKn <
710 MHz
40
—
60
%
Output Clocks (Single-Ended)
Frequency
fOUT
CMOS
5
—
200
MHz
SSTL, HSTL
5
—
350
MHz
CMOS 20%-80%
Rise/Fall Time
tR/tF
2 pF load
—
0.45
0.85
ns
CMOS 20%-80%
Rise/Fall Time
tR/tF
15 pF load
—
2.0
ns
CMOS Output
Resistance
—50
—
SSTL Output Resistance
—50
—
HSTL Output Resistance
—50
—
CMOS Output Voltage
VOH
4 mA load
VDDO–0.3
—
V
VOL
4 mA load
—
0.3
V
SSTL Output Voltage
VOH
SSTL-3 VDDOx = 2.97 to
3.63 V
0.45xVDDO+0.41
—
V
VOL
——
0.45xVDDO
–0.41
V
VOH
SSTL-2 VDDOx = 2.25 to
2.75 V
0.5xVDDO+0.41
—
V
VOL
——
0.5xVDDO–
0.41
V
VOH
SSTL-18 VDDOx = 1.71
to 1.98 V
0.5xVDDO+0.34
—
V
VOL
——
0.5xVDDO–
0.34
V
Table 4. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units