參數(shù)資料
型號: SI5330L-A00230-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 4/20頁
文件大?。?/td> 0K
描述: IC CLK BUFFER TRANSLA 1:4 24-QFN
標(biāo)準(zhǔn)包裝: 490
類型: 扇出緩沖器(分配),變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/是
輸入: CMOS,HSTL,LVTTL,SSTL
輸出: LVDS
頻率 - 最大: 350MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 托盤
Si5330
12
Rev. 1.1
14
CLK2A
O
Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK2 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK2 outputs. Both
CLK2A and CLK2B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
15
VDDO2
VDD
Supply
Output Clock Supply Voltage.
Supply voltage for CLK2A/B. Use a 0.1 F bypass cap
as close as possible to this pin. If CLK2 is not used, this
pin must be tied to VDD (pin 7 and/or pin 24).
16
VDDO1
VDD
Supply
Output Clock Supply Voltage.
Supply voltage for CLK1A,B. Use a 0.1 F bypass cap
as close as possible to this pin. If CLK1 is not used, this
pin must be tied to VDD (pin 7 and/or pin 24).
17
CLK1B
O
Multi
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
18
CLK1A
O
Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
19
OEB
I
CMOS
Output Enable.
All outputs are enabled when the OEB pin is connected
to ground or below the VIL voltage for this pin. Connect-
ing the OEB pin to VDD or above the VIH level will dis-
able the outputs. Both VIL and VIH are specified in
Table 5. All outputs are forced to a logic “l(fā)ow” when dis-
abled. This pin is 3.3 V tolerant.
20
VDDO0
VDD
Supply
Output Clock Supply Voltage.
Supply voltage for CLK0A,B. Use a 0.1 F bypass cap
as close as possible to this pin. If CLK2 is not used, this
pin must be tied to VDD (pin 7 and/or pin 24).
Table 10. Si5330 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
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