Figure 9. I2C Programming Procedure Register Map Use ClockBui" />
參數(shù)資料
型號(hào): SI5338P-A-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 15/44頁
文件大小: 0K
描述: IC CLK GEN I2C BUS PROG 24QFN
標(biāo)準(zhǔn)包裝: 490
系列: MultiSynth™
類型: *
PLL:
輸入: CML,HCSL,HSCL,LVDS,LVPECL,晶體
輸出: CMOS,HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 350MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 托盤
Si5338
22
Rev. 1.3
Figure 9. I2C Programming Procedure
Register
Map
Use ClockBuilder
Desktop v3.0 or later
Pause LOL
Set DIS_LOL = 1; reg241[7]
Write new configuration to device
accounting for the write-allowed mask
(See Si5338 Reference Manual)
Validate input clock status
Disable Outputs
Set OEB_ALL = 1; reg230[4]
NO
YES
Input clocks are
validated with the
LOS alarms. See
Register 218 to
determine which LOS
should be monitored
Configure PLL for locking
Set FCAL_OVRD_EN = 0; reg49[7]
Initiate Locking of PLL
Set SOFT_RESET = 1; reg246[1]
Wait 25 ms
Restart LOL
Set DIS_LOL = 0; reg241[7]
Set reg 241 = 0x65
Is input clock valid?
Confirm PLL lock status
NO
YES
PLL is locked when
PLL_LOL, SYS_CAL, and
all other alarms are
cleared
Copy registers as follows:
237[1:0] to 47[1:0]
236[7:0] to 46[7:0]
235[7:0] to 45[7:0]
Set 47[7:2] = 000101b
Copy FCAL values to
active registers
Set PLL to use FCAL values
Set FCAL_OVRD_EN = 1; reg49[7]
Is PLL locked?
If using down-spread:
Set MS_RESET=1: reg 226[2]=1
Wait 1 ms
Set MS_RESET=0: reg 226[2]=0
Enable Outputs
Set OEB_ALL = 0; reg230[4]
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