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參數(shù)資料
| 型號： | SI5338P-A-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 27/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN I2C BUS PROG 24QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | MultiSynth™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CML，HCSL，HSCL，LVDS，LVPECL，晶體 |
| 輸出： | CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 350MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 托盤 |
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Si5338
Rev. 1.3
33
3IN3
I
Multi
This pin can have one of the following functions depending on the
part number:
CLKIN (for Si5338A/B/C and Si5338N/P/Q devices only)
Provides a high-impedance clock input for single ended clock
signals. This input should be dc-coupled as shown in “3.2. Input
If this pin is not used, it should be connected to ground.
PINC (for Si5338D/E/F devices only)
Used as the phase increment pin. See "3.10.2. Output Phase
Increment/Decrement" on page 26 for more details. Minimum
pulse width of 100 ns is required for proper operation. If this pin is
not used, it should be connected to ground.
FINC (for Si5338G/H/J devices only)
Used as the frequency increment pin. See "3.10.1. Frequency
Increment/Decrement" on page 26 for more details. Minimum
pulse width of 100 ns is required for proper operation. If this pin is
not used, it should be connected to ground.
OEB (for Si5338K/L/M devices only)
Used as an output enable pin. 0 = All outputs enabled; 1 = All
outputs disabled. By default, outputs are tri-stated when disabled.
4IN4
I
Multi
This pin can have one of the following functions depending on the
part number
I2C_LSB (for Si5338A/B/C and Si5338K/L/M devices only)
This is the LSB of the Si5338 I2C address. 0 = I2C address
70h (111 0000), 1 = I2C address 71h (111 0001).
FDBK (for Si5338N/P/Q devices only)
Provides a high-impedance feedback input for single-ended clock
signals. This input should be dc-coupled as shown in “3.2. Input
Stage”, Figure 3. If this pin is not used, it should be connected to
ground.
PDEC (for Si5338D/E/F) devices only)
Used as the phase decrement pin. See “3.10.2. Output Phase
Increment/Decrement” for more details. Minimum pulse width of
100 ns is required for proper operation. If this pin is not used, it
should be connected to ground.
FDEC (for Si5338G/H/J devices only)
Used as the frequency decrement pin. See “3.10.1. Frequency
Increment/Decrement” for more details. Minimum pulse width of
100 ns is required for proper operation. If this pin is not used, it
should be connected to ground.
Table 16. Si5338 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338P-A-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C Program Clk Gen 0.16-350MHz 4Clk In RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338P-B01199-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338P-B01574-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338P-B01574-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338P-B01597-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
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