參數(shù)資料
型號(hào): SI5365-C-GQR
廠商: Silicon Laboratories Inc
文件頁數(shù): 8/28頁
文件大小: 0K
描述: IC CLOCK MULTIPLIER PROG 100TQFP
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時(shí)鐘乘法器
PLL:
輸入: 時(shí)鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.05GHz
除法器/乘法器: 無/是
電源電壓: 1.71 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 帶卷 (TR)
Si5365
16
Rev. 0.5
9C1B
O
LVCMOS
CKIN1 Invalid Indicator.
This pin is an active high alarm output associated with CKIN1. Once
triggered, the alarm will remain high until CKIN1 is validated.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
C2B
O
LVCMOS
CKIN2 Invalid Indicator.
This pin is an active high alarm output associated with CKIN2. Once
triggered, the alarm will remain high until CKIN2 is validated.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
11
C3B
O
LVCMOS
CKIN3 Invalid Indicator.
This pin is an active high alarm output associated with CKIN3.
0 = No alarm on CKIN3.
1 = Alarm on CKIN3.
12
ALRMOUT
O
LVCMOS
Alarm Output Indicator.
This pin is an active high alarm output associated with CKIN4 or the
frame sync alignment alarm.
0 = ALRMOUT not active.
1 = ALRMOUT active.
13
57
CS0_C3A
CS1_C4A
I/O
LVCMOS
Input Clock Select/CKINn Active Clock Indicator.
Input: If manual clock selection mode is chosen (AUTOSEL = 1), the
CS[1:0] pins function as the manual input clock selector control.
These inputs are internally deglitched to prevent inadvertent
clock switching during changes in the CSn input state. If con-
figured as input, these pins must not float.
Output: If automatic clock detection is chosen (AUTOSEL = M or H),
these pins function as the CKINn active clock indicator output.
0 = CKINn is not the active input clock.
1 = CKINn is currently the active input clock to the PLL.
This pin has a weak pulldown.
22
AUTOSEL
I
3-Level
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selection to be
used.
L = Manual.
M = Automatic non-revertive.
H = Automatic revertive.
This pin has a weak pullup and weak pulldown and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
29
30
CKIN4+
CKIN4–
IMULTI
Clock Input 4.
Differential clock input. This input can also be driven with a single-
ended signal.
Table 6. Si5365 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
CS[1:0]
Active Input Clock
00
CKIN1
01
CKIN2
10
CKIN3
11
CKIN4
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SI5366-B-GQR 制造商:Silicon Laboratories Inc 功能描述:
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