參數(shù)資料
型號： SI5365-C-GQR
廠商： Silicon Laboratories Inc
文件頁數(shù)： 9/28頁
文件大?。?/td> 0K
描述： IC CLOCK MULTIPLIER PROG 100TQFP
標準包裝： 250
系列： DSPLL®
類型： 時鐘乘法器
PLL： 是
輸入： 時鐘
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 4:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.05GHz
除法器/乘法器： 無/是
電源電壓： 1.71 V ~ 2.75 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP
供應商設備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
Si5365
Rev. 0.5
17
34
35
CKIN2+
CKIN2–
IMULTI
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal.
37
DBL2_BY
I
3-Level
CKOUT2 Disable/PLL Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and PLL bypass
mode.
L = CKOUT2 Enabled.
M = CKOUT2 Disabled.
H = BYPASS Mode with CKOUT2 enabled. Bypass is not available with
CMOS outputs.
This pin has a weak pullup and weak pulldown and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
39
40
CKIN3+
CKIN3–
IMULTI
Clock Input 3.
Differential clock input. This input can also be driven with a single-
ended signal.
44
45
CKIN1+
CKIN1–
IMULTI
Clock Input 1.
Differential clock input. This input can also be driven with a single-
ended signal.
50
DBL5
I
3-Level
CKOUT5 Disable.
This pin performs the following functions:
L = Normal operation. Output path is active and signal format is deter-
mined by SFOUT inputs.
M = CMOS signal format. Overrides SFOUT signal format to allow
CKOUT5 to operate in CMOS format while the clock outputs operate in
a differential output format.
H = Powerdown. Entire CKOUT5 divider and output buffer path is pow-
ered down. CKOUT5 output will be in tristate mode during powerdown.
This pin has a weak pullup and weak pulldown and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
56
FOS_CTL
I
3-Level
Frequency Offset Control.
This pin enables or disables use of the CKIN2 FOS reference as an
input to the clock selection state machine.
L = FOS Disabled.
M = Stratum 3/3E FOS Threshold.
H = SONET Minimum Clock FOS Threshold.
This pin has both weak pullups and weak pulldowns and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
58
C1A
O
LVCMOS
CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator.
0 = CKIN1 is not the active input clock.
1 = CKIN1 is currently the active input clock to the PLL.
59
C2A
O
LVCMOS
CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator.
0 = CKIN2 is not the active input clock.
1 = CKIN2 is currently the active input clock to the PLL.
Table 6. Si5365 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
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相關代理商/技術參數(shù)
參數(shù)描述
SI5365-EVB 制造商:Silicon Laboratories Inc 功能描述:
SI5366 制造商:SILABS 制造商全稱:SILABS 功能描述:PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Si5366-B-GQ 功能描述:鎖相環(huán) - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
SI5366-B-GQR 制造商:Silicon Laboratories Inc 功能描述:
Si5366-C-GQ 功能描述:鎖相環(huán) - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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