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參數(shù)資料
| 型號： | SII141B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Box-shaped pin header, Discrete wire crimping connection, Discrete wire connectors; HRS No: 536-0101-9 00; No. of Positions: 2; Connector Type: Board mounting; Contact Gender: Male; Contact Spacing (mm): 1.25; Terminal Pitch (mm): 1.25; PCB Mount Type: Through-hole; Current Rating(Amps)(Max.): 1; Contact Mating Area Plating: Tin; Operating Temperature Range (degrees C): -35 to 85; General Description: Header; Straight; Single row |
| 中文描述： | 精工141B章PanelLink數(shù)字接收機 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 84K |
| 代理商： | SII141B |
AC Specifications
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below.
Symbol
Parameter
T
DPS
Intra-Pair (+ to -) Differential Input Skew
SiI 141B
SiI-DS-0037-C
Silicon Image, Inc.
4
Subject to Change without Notice
Conditions
86 MHz
86 MHz
65 MHz
86 MHz
C
L
= 10pF; ST = 1
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
Min
Typ
Max
470
7
465
350
3.5
4.5
3.5
4.5
1.6
2.1
1.6
2.1
3.0
4.2
3.0
4.2
1.5
1.9
1.5
1.9
Units
ps
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
CCS
Channel to Channel Differential Input Skew
T
IJIT
Worst Case Differential Input Clock Jitter tolerance
1,2
Low-to-High Transition Time: Data and Controls
(43 MHz, 2-pixel/clock, PIXS=1)
Low-to-High Transition Time: Data and Controls
(65 MHz, 1-pixel/clock, PIXS=0)
Low-to-High Transition Time: ODCK
(43 MHz, 2-pixel/clock, PIXS=1)
Low-to-High Transition Time: ODCK
(65 MHz, 1-pixel/clock, PIXS=0)
High-to-Low Transition Time: Data and Controls
(43 MHz, 2-pixel/clock, PIXS=1)
High-to-Low Transition Time: Data and Controls
(65 MHz, 1-pixel/clock, PIXS=0)
High-to-Low Transition Time: ODCK
(43 MHz, 1-pixel/clock, PIXS=0)
High-to-Low Transition Time: ODCK
(65 MHz, 1-pixel/clock, PIXS=0)
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to
ODCK falling edge (OCK_INV = 0) or to ODCK rising
edge (OCK_INV = 1)
*OCK_INV = 1
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from
ODCK falling edge, (OCK_INV = 0) or from ODCK rising
edge (OCK_INV = 1)
*OCK_INV = 0
ODCK Cycle Time (1 pixel/clock)
ODCK Frequency (1 pixel/clock)
ODCK Cycle Time (2 pixels/clock)
ODCK Frequency (2 pixels/clock)
ODCK High Time
65 MHz, One Pixel / Clock, PIXS = 0
3
43 MHz, Two Pixel / Clock, PIXS = 1
3
D
LHT
D
HLT
T
SETUP
3.6
3.0*
18.4
19.0*
8.0
8.4*
24.0
24.5*
11.6
25
23.3
12.5
5.0
4.4
9.0
8.2
6
5
9
9
C
L
= 5pF; ST = 0
T
HOLD
C
L
= 10pF; ST = 1
ns
C
L
= 5pF; ST = 0
ns
R
CIP
F
CIP
R
CIP
F
CIP
R
CIH
C
L
= 10pF, ST=1
C
L
= 5pF, ST=0
C
L
= 10pF, ST=1
C
L
= 5pF, ST=0
C
L
= 10pF, ST=1
C
L
= 5pF, ST=0
C
L
= 10pF, ST=1
C
L
= 5pF, ST=0
40
86
80
43
ns
MHz
ns
MHz
ns
ns
R
CIL
ODCK Low Time
65 MHz, One Pixel / Clock, PIXS = 0
3
43 MHz, Two Pixel / Clock, PIXS = 1
3
ns
ns
T
HSC
T
FSC
Link disabled (DE inactive) to SCDT low
1
Link disabled (Tx power down) to SCDT low
5
Link enabled (DE active) to SCDT high
160
200
ms
ms
Falling
DE edges
μ
s
μ
s
ns
250
40
10
100
8
T
CLKPD
T
CLKPU
T
PDL
Notes:
Delay from RXC+/- Inactive to high impedance outputs
Delay from RXC+/- active to data active
Delay from PD/ PDO Low to high impedance outputs
1
Jitter defined as per DVI 1.0 Specification, Section 4.6
Jitter Specification
.
2
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7
Electrical Measurement Procedures
.
3
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
4
The setup and hold timing for the data and controls relative to the ODCK rising edge (OCK_INV=1) is by design the same
as the falling edge timing.
5
Measured when transmitter was powered down (see Si
I
/AN-0005 “PanelLink Basic Design /Application Guide,” Section 2.4).
6
Refer to the transmitter datasheet for minimum DE high and low time
7
Data is active (i.e. not tri-stated) but not valid yet. Data and controls are valid only when SCDT goes high. See T
FSC
and
Figure 7.
RXC+/- = 25MHz
RXC+/- = 25MHz
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