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參數(shù)資料
| 型號： | SII150A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PanelLink Digital Transmitter |
| 中文描述： | PanelLink數(shù)字發(fā)射機(jī) |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 73K |
| 代理商： | SII150A |
Silicon Image, Inc.
SiI 150A
SiI/DS-0006-C
Revision C
3
Subject to Change without Notice
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
T
CIP
IDCK Period, 1 Pixel/Clock
F
CIP
IDCK Frequency, 1 Pixel/Clock
T
CIP
IDCK Period, 2 Pixels/Clock
F
CIP
IDCK Frequency, 2 Pixels/Clock
T
CIH
IDCK High Time at 112MHz
T
CIL
IDCK Low Time at 112MHz
T
IJIT
Worst Case IDCK Clock Jitter
T
SIDF
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Setup Time to IDCK falling edge
T
HIDF
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Hold Time from IDCK falling edge
T
SIDR
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Setup Time to IDCK rising edge
T
HIDR
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Hold Time from IDCK rising edge
T
DDF
VSYNC, HSYNC, and CTL[3:1] Delay from DE falling edge
T
DDR
VSYNC, HSYNC, and CTL[3:1] Delay to DE rising edge
T
HDE
DE high time
T
LDE
DE low time
Conditions
Min
8.93
20
17.8
10
4
4
Typ
Max
50
112
100
56
Units
ns
MHz
ns
MHz
ns
ns
ns
ns
2,3
2
EDGE = 0
1
EDGE = 0
3
ns
EDGE = 1
1
ns
EDGE = 1
3
ns
1
T
CIP
T
CIP
ns
ns
ns
ns
1
1
8191T
CIP
1
128T
CIP
0.25
S
LHT
Small Swing Low-to-High
Transition Time
C
LOAD
= 5pF
R
LOAD
= 50
R
EXT_SWING
= 510
C
LOAD
= 5pF
R
LOAD
= 50
R
EXT_SWING
= 510
0.3
0.35
ns
S
HLT
Small Swing High-to-Low
Transition Time
0.25
0.3
0.35
ns
Notes:
1
Guaranteed by design.
Jitter can be estimated by 1) triggering a digital scope at the rising of input clock and 2) measuring the peak to peak time spread
of the rising edge of the input clock 1
μ
s after the trigger.
Actual jitter tolerance may be higher depending on the frequency of the jitter.
2
3
Timing Diagrams
T
CIH
T
CIL
T
CIP
2.0 V
0.8 V
0.8 V
2.0 V
2.0 V
Figure 1. Clock Cycle/High/Low Times
Figure 2. Small Swing Transition Times
S
LHT
20% V
OD
80% V
OD
S
HLT
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