參數(shù)資料
型號(hào): TLV1562CPWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: 0.65 MM PITCH, GREEN, TSSOP-28
文件頁(yè)數(shù): 6/41頁(yè)
文件大小: 600K
代理商: TLV1562CPWG4
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
mono interrupt-driven mode (CR0.(3,2) = 0,0)
The mono interrupt-driven conversion mode provides a one-shot conversion. Sampling, conversion, and data
output are all performed in a single cycle. The analog signal is sampled 2 SYSCLKs after the falling edge of RD
(or the rising edge of WR if this is the first sample after configuration) and then converted on the falling edge
of RD. Once the data is ready, INT falls and the data is output to the bus. The rising edge of RD cancels INT
and initiates a read of the data. The data bus is 3-stated when RD goes high. It is not necessary to configure
the converter for each cycle or toggle CS between cycles.
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
t s1
t
t s1
t conv1
t d(RDL-SAMPLE)
t d(RDL-CONV)
Hi–Z
t en(DATAOUT)
t d(CONV-INTL)
t (APD)
t dis(DATAOUT)
t d(RDH-INTZ)
Power Down
(If Autopower Down is Set)
Power Down
(If Autopower Down is Set)
CS
CSTART
WR
RD
DATA
INT
conv1
Data 1
Sample 1
Conv 1
Sample 2
Conv 2
(With Pullup)
t 1(APDR)
Figure 11. Mono Interrupt-Driven Mode Using RD
相關(guān)PDF資料
PDF描述
TLV1562IDWG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IDW 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IPWG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562CPWLE 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IPWLE 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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