參數(shù)資料
型號(hào): TLV1562CPWG4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): ADC
英文描述: 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: 0.65 MM PITCH, GREEN, TSSOP-28
文件頁(yè)數(shù): 38/41頁(yè)
文件大小: 600K
代理商: TLV1562CPWG4
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
Table 1. Select Input Channels
CR0.4
(INPUT TYPE)
CR0.(3,2)
(CONVERSION MODE
SELECT)
CR0.(1,0)
(CHANNEL SELECT)
CHANNEL(S)
SELECTED
NOTE
0 (Single-ended)
00 or 10
0,0
CH1
Single channel
0 (Single-ended)
00 or 10
0,1
CH2
Single channel
0 (Single-ended)
00 or 10
1,0
CH3
Single channel
0 (Single-ended)
00 or 10
1,1
CH4
Single channel
1 (Differential)
00 or 10
0,X
Differential pair A
Single channel
1 (Differential)
00 or 10
1,X
Differential pair B
Single channel
0 (Single-ended)
01 or 11
X,0
Both CH1 and CH3
Dual channels
0 (Single-ended)
01 or 11
X,1
Both CH2 and CH4
Dual channels
0 (Single-ended)
01 or 11
X,0
Both CH1 and CH3
Dual channels
0 (Single-ended)
01 or 11
X,1
Both CH2 and CH4
Dual channels
1 (Differential)
01 or 11
X,X
Both differential pairs A and B
Dual channels
configure the device
The device can be configured by writing to control registers CR0 and CR1. A read register is carried out by
auto-sequence when the device is put into the software power-down state. CR0 is read first and then CR1 at
the next two RD rising edges after the device is in the software power-down state. The falling edge of RD has
no meaning and does not trigger a conversion in the software power-down state.
VIH
VIL
VIH
VIL
CS
CSTART
WR
DATA
td(CSL-WRL)
tw(CSH)
td(WRH-CSH)
VIH
VIL
ts(DATAIN)
tw(WRL)
th(DATAIN)
Configure Data
Figure 2. Configuration Cycle Timing
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