參數(shù)資料
型號(hào): TLV1562CPWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: 0.65 MM PITCH, GREEN, TSSOP-28
文件頁數(shù): 7/41頁
文件大?。?/td> 600K
代理商: TLV1562CPWG4
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Conversion can also be started with CSTART. This is useful when an application requires multiple TLV1562s
for simultaneous samplings and conversions. The falling edge of CSTART starts the sampling and the rising
edge of CSTART starts the conversion. Once the data is ready INT falls. INT is terminated by the following falling
edge of RD which also outputs the data to the bus. On the rising edge of RD, the data is read and the data bus
is 3-stated.
t (APD)
Power Down
(If Autopower Down is Set)
Power Down
t dis(DATAOUT)
t d1(WRH–CSTARTL)
t w(CSTARTL)
t d(CSL-RDL)
t d(RDH-CSTARTL)
t s1
t conv1
t w(RDL)
t s1
t d(CSTART-SAMPLE)
t d(INTL-CSL)
t en(DATAOUT)
t d(CSTARTL-SAMPLE)
t d(RDH-INTZ)
t d(CONV-INTL)
t d1(CSTARTH–CONV)
VIH
VIL
CS
CSTART
WR
RD
DATA
INT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Data 1
(With Pullup)
Sample 1
Conv 1
Sample 2
t 1(APDR)
Figure 12. Mono Interrupt-Driven Mode Using CSTART
相關(guān)PDF資料
PDF描述
TLV1562IDWG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IDW 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562IPWG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV1562CPWLE 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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