參數(shù)資料
型號: SKY72300-362
廠商: Skyworks Solutions Inc
文件頁數(shù): 2/20頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER 2.1GHZ 24QFN
產(chǎn)品目錄繪圖: 24-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 分?jǐn)?shù) N 合成器
PLL:
輸入: 時鐘,晶體
輸出: 時鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 587 (CN2011-ZH PDF)
其它名稱: 863-1077-6
DATA SHEET SKY72300-362 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
10
July 30, 2007 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 200731B
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
X
MSB
LSB
Main Synthesizer Divider Index
C1417
Figure 6. Main Divider Register (Write Only)
C1418
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
1
X
MSB
LSB
Main Synthesizer Dividend (MSBs)
Figure 7. Main Dividend MSB Register (Write Only)
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
1
0
X
MSB
LSB
Main Synthesizer Dividend (LSBs)
C1419
Figure 8. Main Dividend LSB Register (Write Only)
Auxiliary Synthesizer Registers
The Auxiliary Divider Register contains the integer portion closest
to the desired fractional-N (or integer-N) value minus 32 for the
auxiliary synthesizer. This register, in conjunction with the
Auxiliary Dividend Register (which controls the fraction offset from
–0.5 to +0.5), allows selection of a precise frequency. As shown
in Figure 9, the value to be loaded is:
Auxiliary Synthesizer Divider Index = Nine-bit value for the integer
portion of the auxiliary synthesizer dividers. Valid values for this
register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-
N).The Auxiliary Dividend Register controls the fraction part of the
desired fractional-N value and allows an offset of –0.5 to +0.5 to
the auxiliary integer selected through the Auxiliary Divider
Register. As shown Figure 10, the value to be loaded is:
Auxiliary Synthesizer Dividend = Ten-bit value for the auxiliary
synthesizer dividend.
General Synthesizer Registers
The dual-programmable reference frequency dividers provide the
reference frequencies to the phase detectors by dividing the
crystal oscillator frequency. The lower five bits hold the reference
frequency divide index for the main phase detector. The next five
bits hold the reference frequency divide index for the auxiliary
phase detector. Divide ratios from 1 to 32 are possible for each
reference frequency divider (see Tables 2 and 3).
The Reference Frequency Dividers Register configures the dual-
programmable reference frequency dividers for the main and
auxiliary synthesizers. As shown in Figure 11, the values to be
loaded are:
Main Reference Frequency Divider Index = Desired main
oscillator frequency division ratio –1. Default value on power up
is 0, signifying that the reference frequency is not divided for
the main phase detector.
Auxiliary Reference Frequency Divider Index = Desired auxiliary
oscillator frequency division ratio –1. Default value on power up
is 0, signifying that the reference frequency is not divided for
the auxiliary phase detector.
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