參數(shù)資料
型號(hào): SKY72300-362
廠商: Skyworks Solutions Inc
文件頁數(shù): 4/20頁
文件大小: 0K
描述: IC SYNTHESIZER 2.1GHZ 24QFN
產(chǎn)品目錄繪圖: 24-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 分?jǐn)?shù) N 合成器
PLL:
輸入: 時(shí)鐘,晶體
輸出: 時(shí)鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 587 (CN2011-ZH PDF)
其它名稱: 863-1077-6
DATA SHEET SKY72300-362 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
12
July 30, 2007 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 200731B
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
01
XX
Main Reference Frequency Divider Index
Auxiliary Reference Frequency Divider Index
C1422
Figure 11. Reference Frequency Dividers Register (Write Only)
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
01
10
Main Phase Detector Gain
Main Power Steering/Lock Detect Enable
Auxiliary Phase Detector Gain
Auxiliary Power Steering/Lock Detect Enable
C1423
Figure 12. Phase Detector/Charge Pump Control Register (Write Only)
The Phase Detector/Charge Pump Control Register allows control
of the gain for both phase detectors and configuration of the
LD/PSmain and LD/PSaux signals for frequency power steering or
lock detection. As shown in Figure 12, the values to be loaded
are:
Main Phase Detector Gain = Five-bit value for programmable
main phase detector gain. Range is from 0 to 31 decimal for
31.25 to 1000
A/ 2π radian, respectively.
Main Power Steering Enable = One-bit flag to enable the
frequency power steering circuitry of the main phase detector.
When this bit is cleared, the LD/PSmain pin is configured to be
a lock detect, active low, open collector pin. When this bit is set,
the LD/PSmain pin is configured to be a frequency power
steering pin and can be used to bypass the external main loop
filter to provide faster frequency acquisition.
Auxiliary Phase Detector Gain = Five-bit value for
programmable auxiliary phase detector gain. Range is from 0 to
31 decimal for 31.25 to 1000
A/2π radians, respectively.
Auxiliary Power Steering Enable = One-bit flag to enable the
frequency power steering circuitry of the auxiliary phase
detector. When this bit is cleared, the LD/PSaux pin is
configured to be a lock detect, active low, open collector pin.
When this bit is set, the LD/PSaux pin is configured to be a
frequency power steering pin and may be used to bypass the
external auxiliary loop filter to provide faster frequency
acquisition.
The Power Down/Multiplexer Output Select Control Register
allows control of the power-down modes, internal multiplexer
output, and main
Σ synthesizer fractionality. As shown in
Figure 13, the values to be loaded are:
Full Power Down = One-bit flag to power down the SKY72300-
362 except for the reference oscillator and the serial interface.
When this bit is cleared, the SKY72300-362 is powered up.
When this bit is set, the SKY72300-362 is in full power-down
mode excluding the Mux_out signal (pin 24).
Main Synthesizer Power Down = One-bit flag to power down
the main synthesizer. When this bit is cleared, the main
synthesizer is powered up. When this bit is set, the main
synthesizer is in power-down mode.
Main Synthesizer Mode = One-bit flag to power down the main
synthesizer’s
Σ modulator and fractional unit to operate as an
integer-N synthesizer. When this bit is cleared, the main
synthesizer is in fractional-N mode. When this bit is set, the
main synthesizer is in integer-N mode.
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