參數(shù)資料
型號(hào): SL23EP04SI-2HT
廠商: Silicon Laboratories Inc
文件頁數(shù): 4/15頁
文件大?。?/td> 0K
描述: IC BUFFER 220MHZ 4CH 3.3V 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: EProClock®
類型: *
PLL:
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/無
頻率 - 最大: 220MHz
除法器/乘法器: 是/是
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
May 15, 2008
Page 12 of 15
SL23EP04
Switching Electrical Characteristics (I-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Description
Symbol
Condition
Min
Typ
Max
Unit
Output Frequency Range
FOUT1
CL=15pf, -1H and -2H versions
10
-
170
MHz
FOUT2
CL=22pf, -1H and -2H versions
10
-
135
MHz
FOU3
CL=30pF, -1H and -2H versions
10
-
100
MHz
FOUT4
CL=15pf, -1 and -2 versions
10
-
135
MHz
FOUT5
CL=22pf, -1 and -2 versions
10
-
100
MHz
FOUT6
CL=30pf, -1 and -2 versions
10
-
75
MHz
Input Duty Cycle
DC1
Measured at VDD/2, all versions
40
50
60
%
Output Duty Cycle
DC2
CL=30pF, Fout=66 MHz, all versions
Measured at VDD/2
40
50
60
%
Output Duty Cycle
DC3
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
45
50
55
%
Output Duty Cycle
DC4
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
45
50
55
%
Output Duty Cycle
DC5
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
40
50
60
%
Output Rise/Fall Time
tr/f1
CL=30pF, -1 and -2 versions
Measured at 0.6 to 1.8V
-
3.2
ns
Output Rise/Fall Time
tr/f2
CL=15pF, -1 and -2 versions
Measured at 0.6 to 1.8V
-
2.0
ns
Output Rise/Fall Time
tr/f3
CL=30pF, -1H and -2H versions
Measured at 0.6 to 1.8V
-
2.0
ns
Output Rise/Fall Time
tr/f4
CL=15pF, -1H and -2H version
Measured at 0.6 to 1.8V
-
1.5
ns
Output-to-Output Skew
on Same Bank
SKW1
-1 and -2, measured at VDD/2, and
outputs are equally loaded
-
100
220
ps
Output-to-Output Skew
on Same Bank
SKW2
-1H and -2H, measured at VDD/2 and
outputs are equally loaded
-
100
220
ps
Output-to-Output Skew
Between Bank A and B
SKW3
-1 and -2, measured at VDD/2, and
outputs are equally loaded
-
100
220
ps
Output-to-Output Skew
Between Bank A and B
SKW4
-1H and -2H, measured at VDD/2 and
outputs are equally loaded
-
180
375
ps
Device-to-Device Skew
SKW5
All versions, measured at VDD/2 and
outputs are equally loaded
-
225
550
ps
Input-to-Output Delay
Dt
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded
-300
+/-125
300
ps
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