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參數(shù)資料
| 型號(hào)： | SL23EP04SI-2HT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER 220MHZ 4CH 3.3V 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | EProClock® |
| 類(lèi)型： | * |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 220MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
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May 15, 2008
Page 13 of 15
SL23EP04
Switching Electrical Characteristics (I-Grade and VDD=2.5V – Cont.)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Cycle-to-Cycle Jitter
(-1 and -2 Versions)
CCJ1
Fout=66.6 MHz and CL=15pF
-
150
ps
Fout=133.3 MHz and CL=15pF
-
150
ps
Cycle-to-Cycle Jitter
(-1H and -2H Versions)
CCJ2
Fout=66.6 MHz and CL=15pF
-
400
ps
Fout=166.6 MHz and CL=15pF
-
400
ps
PLL Lock Time
tLOCK
From 0.95VDD and valid CLKIN
-
1.0
ms
External Components & Design Considerations
Typical Application Schematic
SL23EP04
CL
0.1
μF
CLKIN
FBK
CLKA1
GND
VDD
1
7
4
3
2
8
CL
CLKA2
CL
CLKB2
CL
CLKB1
5
6
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and
to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD
pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output
clocks and the load is over 1 inch. The nominal impedance of the clock outputs is given in the Operating Condition
Tables. Place the series termination resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero
Delay” between the CLKIN and the outputs. The FBK pin is connected to PLL internally on-chip for feedback and
should be connected to one of to output clocks externally. For applications requiring zero input/output delay, the load
at the all output pins including the FBK pin must be the same. If any delay adjustment is required, the capacitance at
the FBK pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks
relative to CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
In addition, the rise and fall time of the reference clock at CLKIN pin should be similar to rise and fall times at the
CLKA and CLK B bank outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL23EP04SI-2T | 功能描述:時(shí)鐘緩沖器 10-220MHz 4 Outputs ZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05 | 制造商:SPECTRALINEAR 制造商全稱(chēng):SPECTRALINEAR 功能描述:Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB) |
| SL23EP05SC-1 | 功能描述:時(shí)鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SC-1H | 功能描述:時(shí)鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V Hi Drv RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SC-1HT | 功能描述:時(shí)鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V Hi Drv RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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