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參數(shù)資料
| 型號： | SL28610BLIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 3/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK ATOM POULSBO PCIE 48QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
SL28610
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 11 of 23
Byte 20: Control Register 20
Byte 21: Control Register 21
CKPWRGD#/PD (Power down) Clarification
The CKPWRGD#/PD pin is a dual-function pin. During initial
power
up,
the
pin
functions
as
CKPWRGD#.
Once
CKPWRGD# has been sampled HIGH by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD is also an asynchronous input for powering up
the system. When PD is asserted HIGH, clocks are driven to
a LOW value and held before turning off the VCOs and the
crystal oscillator.
CKPWRGD#/PD (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held HIGH on their
next HIGH-to-LOW transition and differential clocks must held
HIGH. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10
s after asserting
CKPWRGD.
CKPWRGD#/PD (Power Down) Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300
s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
Bit
@Pup
Name
Description
7
0
PLL3_DAF_N7
If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and
PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.
6
0
PLL3_DAF_N6
5
0
PLL3_DAF_N5
4
0
PLL3_DAF_N4
7
0
PLL3_DAF_N3
2
0
PLL3_DAF_N2
1
0
PLL3_DAF_N1
0
PLL3_DAF_N0
Bit
@Pup
Name
Description
7
0
PLL3_DAF_M7
If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and
PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.
6
0
PLL3_DAF_M6
5
0
PLL3_DAF_M5
4
0
PLL3_DAF_M4
7
0
PLL3_DAF_M3
2
0
PLL3_DAF_M2
1
0
PLL3_DAF_M1
0
PLL3_DAF_M0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL28610BLITR | 制造商:Silicon Laboratories Inc 功能描述: |
| SL28647BLC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28647BLCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28647CLC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28647CLCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Montevina RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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