- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9619 > SL28773ELIT (Silicon Laboratories Inc)IC CLOCK CK505 PCIE INTEL 32QFN PDF資料下載
參數(shù)資料
| 型號(hào)： | SL28773ELIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK505 PCIE INTEL 32QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | EProClock® |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 133MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
SL28773
........................Document #: 001-08400 Rev ** Page 3 of 21
PC EProClock Programmable Technology
PC EProClock is the world’s first non-volatile programmable
PC clock. The PC EProClock technology allows board
designer to promptly achieve optimum compliance and clock
signal integrity; historically, attainable typically through device
and/or board redesigns.
PC EProClock technology can be configured through SMBus
or hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
- For more information: Please refer to Application Note #25
Frequency Select Pin FS
Apply the appropriate logic levels to FS inputs before
CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD
and indicates that VTT voltage is stable then FS input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other FS,
and CKPWRGD transitions are ignored except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
.
Frequency Select Pin (FS)
FS
CPU
Power On
SRC
SATA
DOT96
USB_48
27MHz
REF
0
133MHz
Default
100MHz
96MHz
48MHz
27MHz
14.318MHz
1
100MHz
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
1
Start
8:2
Slave address–7 bits
8:2
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code–8 bits
18:11
Command Code–8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count–8 bits
20
Repeat start
28
Acknowledge from slave
27:21
Slave address–7 bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIN208CB-T | IC 4DRVR/4RCVR RS232 5V 24-SOIC |
| HIN208CB | IC 4DRVR/4RCVR RS232 5V 24-SOIC |
| HIN207EIB-T | IC 5DRVR/3RCVR RS232 5V 24-SOIC |
| HIN207EIB | IC 5DRVR/3RCVR RS232 5V 24-SOIC |
| HIN207ECB-T | IC 5DRVR/3RCVR RS232 5V 24-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL28774ELC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Shrink CK505 for Calpella platforms RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28774ELCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Shrink CK505 for Calpella platforms RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28774ELI | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Shrink CK505 for Calpella platforms RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28774ELIT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Shrink CK505 for Calpella platforms RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28779ELC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Calpella IrnLk JpFrt Ibex Pk Add USB28748 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。