參數(shù)資料
型號(hào): SL28774ELIT
廠商: Silicon Laboratories Inc
文件頁數(shù): 11/19頁
文件大?。?/td> 0K
描述: IC CLOCK CK505 CALPELLA 32QFN
標(biāo)準(zhǔn)包裝: 2,500
系列: EProClock®
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無/是
頻率 - 最大: 133MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28774
......................Document #: 001-08400 Rev ** Page 19 of 19
Document History Page
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon
Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of
information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or param-
eters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental
damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or
for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Silicon Laboratories harmless against all claims and damages.
Document Title: SL28774 PC EProClock Generator for Intel Calpella Chipset
REV.
Issue Date
Orig. of
Change
Description of Change
1.0
07/22/08
JMA
Initial Release
1.1
09/08/09
JMA
Removed Preliminary
1.2
10/02/09
JMA
Updated note in package diagram
1.3
01/05/10
JMA
1. Added Note in package diagram
2. Updated text content
3. Added information on trace length in Figure 8
4. Removed CPU Driven Figures
5. Updated VDD_IO spec to 3.465 maximum value
6. Edited CK_PWRGD to CKPWRGD
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