參數(shù)資料
型號(hào)： SL28774ELIT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 6/19頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK CK505 CALPELLA 32QFN
標(biāo)準(zhǔn)包裝： 2,500
系列： EProClock®
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： Intel CPU 服務(wù)器
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:8
差分 - 輸入:輸出： 無/是
頻率 - 最大： 133MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
SL28774
......................Document #: 001-08400 Rev ** Page 14 of 19
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
The device operates reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
XIN Period
When XIN is driven from an external
clock source
69.841
71.0
ns
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-
s duration
–
500
ps
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
9.99900
10.00100
ns
TPERIOD
133 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
7.49925
7.50075
ns
TPERIODSS
100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODSS
133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
7.51804
7.51955
ns
TPERIODAbs
100 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
9.91400
10.0860
ns
TPERIODAbs
133 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
7.41425
7.58575
ns
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential at1 clock
9.914063
10.1362
ns
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential at1 clock
7.41430
7.62340
ns
TCCJ
CPU Cycle to Cycle Jitter
Measured at 0V differential
–
85
ps
Skew
CPU0 to CPU1 skew
Measured at 0V differential
–
100
ps
LACC
Long-term Accuracy
Measured at 0V differential
–
100
ppm
TR / TF
CPU Rising/Falling Slew rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SRC Period
Measured at 0V differential at 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRC Period, SSC
Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz SRC Absolute Period
Measured at 0V differential at 1 clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
Measured at 0V differential at 1 clock
9.87406
10.1762
ns
TSKEW(window) Any SRC Clock Skew from the earliest
bank to the latest bank
Measured at 0V differential
–
3.0
ns
TCCJ
SRC Cycle to Cycle Jitter
Measured at 0V differential
–
125
ps
LACC
SRC Long Term Accuracy
Measured at 0V differential
–
100
ppm
TR / TF
SRC Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
DOT96 at 0.7V
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