參數(shù)資料
型號: SL28SRC01BZIT
廠商: Silicon Laboratories Inc
文件頁數(shù): 7/11頁
文件大?。?/td> 0K
描述: IC CLOCK PCIE GEN3/2 DIF 16TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: *
PLL:
輸入: 時鐘,晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 100MHz
除法器/乘法器: 無/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28SRC01
DOC#: SP-AP-0015 (Rev. 0.2)
Page 5 of 11
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
The device operates reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
XIN Period
When XIN is driven from an external
clock source
69.841
71.0
ns
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-
s duration
500
ps
LACC
Long-term Accuracy
Measured at VDD/2 differential
250
ppm
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
53
%
TR/TF
CLKIN Rise and Fall Times
Measured between 0.2VDD and 0.8VDD
0.5
4.0
V/ns
TCCJ
CLKIN Cycle to Cycle Jitter
Measured at VDD/2
250
ps
TLTJ
CLKIN Long Term Jitter
Measured at VDD/2
350
ps
VIL
Input Low Voltage
XIN / CLKIN pin
0.8
V
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
V
IIL
Input LowCurrent
XIN / CLKIN pin, 0 < VIN <0.8
20
uA
IIH
Input HighCurrent
XIN / CLKIN pin, VIN = VDD
35
uA
SRC
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SRC Period
Measured at 0V differential at 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRC Period, SSC
Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz SRC Absolute Period
Measured at 0V differential at 1 clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
Measured at 0V differential at 1 clock
9.87406
10.1762
ns
TCCJ
SRC Cycle to Cycle Jitter
Measured at 0V differential
50
ps
RMSGEN1
Output PCIe* Gen1 REFCLK phase
jitter
BER = 1E-12 (including PLL BW 8 - 16
MHz, ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz)
0108
ps
RMSGEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.0
ps
RMSGEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.1
ps
RMSGEN3
Output phase jitter impact – PCIe*
Gen3
Includes PLL BW 2 - 4 MHz,
CDR = 10MHz)
01.0
ps
LACC
SRC Long Term Accuracy
Measured at 0V differential
100
ppm
TR / TF
SRC Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
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SL28SRC02BZCTR 制造商:Silicon Laboratories Inc 功能描述:
SL28SRC02BZI 功能描述:時鐘發(fā)生器及支持產(chǎn)品 PCIE Clk Gen Xin 14M -->4 PCIE out Gen3 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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